Merge pull request #19 from austriancoder/master

gc2000: fix RS_PIPE_OFFSET and RS_WINDOW_SIZE

7 files changed, 23 insertions, 12 deletions

diff --git a/src/driver/etna_clear_blit.c b/src/driver/etna_clear_blit.c
index 13a1d9b..1b3b8f8 100644
--- a/src/driver/etna_clear_blit.c
+++ b/src/driver/etna_clear_blit.c
@@ -62,7 +62,7 @@ static void etna_pipe_blit_save_state(struct pipe_context *pipe)
 }
 
 /* Generate clear command for a surface (non-fast clear case) */
-void etna_rs_gen_clear_surface(struct compiled_rs_state *rs_state, struct etna_surface *surf, uint32_t clear_value)
+void etna_rs_gen_clear_surface(struct etna_ctx *ctx, struct compiled_rs_state *rs_state, struct etna_surface *surf, uint32_t clear_value)
 {
     uint bs = util_format_get_blocksize(surf->base.format);
     uint format = 0;
@@ -78,7 +78,7 @@ void etna_rs_gen_clear_surface(struct compiled_rs_state *rs_state, struct etna_s
     bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
                        (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0;
     struct etna_bo *dest_bo = etna_resource(surf->base.texture)->bo;
-    etna_compile_rs_state(rs_state, &(struct rs_state){
+    etna_compile_rs_state(ctx, rs_state, &(struct rs_state){
             .source_format = format,
             .dest_format = format,
             .dest_addr = etna_bo_gpu_address(dest_bo) + surf->surf.offset,
@@ -149,7 +149,7 @@ static void etna_pipe_clear(struct pipe_context *pipe,
             else if(unlikely(new_clear_value != surf->level->clear_value)) /* Queue normal RS clear for non-TS surfaces */
             {
                 /* If clear color changed, re-generate stored command */
-                etna_rs_gen_clear_surface(&surf->clear_command, surf, new_clear_value);
+                etna_rs_gen_clear_surface(priv->ctx, &surf->clear_command, surf, new_clear_value);
             }
             etna_submit_rs_state(priv->ctx, &surf->clear_command);
             surf->level->clear_value = new_clear_value;
@@ -173,7 +173,7 @@ static void etna_pipe_clear(struct pipe_context *pipe,
         } else if(unlikely(new_clear_value != surf->level->clear_value)) /* Queue normal RS clear for non-TS surfaces */
         {
             /* If clear depth value changed, re-generate stored command */
-            etna_rs_gen_clear_surface(&surf->clear_command, surf, new_clear_value);
+            etna_rs_gen_clear_surface(priv->ctx, &surf->clear_command, surf, new_clear_value);
         }
         etna_submit_rs_state(priv->ctx, &surf->clear_command);
         surf->level->clear_value = new_clear_value;
diff --git a/src/driver/etna_clear_blit.h b/src/driver/etna_clear_blit.h
index 097c307..ac5f671 100644
--- a/src/driver/etna_clear_blit.h
+++ b/src/driver/etna_clear_blit.h
@@ -26,11 +26,12 @@
 
 #include <stdint.h>
 
+struct etna_ctx;
 struct pipe_context;
 struct etna_surface;
 struct compiled_rs_state;
 
-void etna_rs_gen_clear_surface(struct compiled_rs_state *rs_state, struct etna_surface *surf, uint32_t clear_value);
+void etna_rs_gen_clear_surface(struct etna_ctx *ctx, struct compiled_rs_state *rs_state, struct etna_surface *surf, uint32_t clear_value);
 
 void etna_pipe_clear_blit_init(struct pipe_context *pipe);
 
diff --git a/src/driver/etna_screen.c b/src/driver/etna_screen.c
index 6a8f2bf..f381c7d 100644
--- a/src/driver/etna_screen.c
+++ b/src/driver/etna_screen.c
@@ -471,7 +471,7 @@ static void etna_screen_flush_frontbuffer( struct pipe_screen *screen,
 
     /* Kick off RS here */
     struct compiled_rs_state copy_to_screen;
-    etna_compile_rs_state(&copy_to_screen, &(struct rs_state){
+    etna_compile_rs_state(ctx, &copy_to_screen, &(struct rs_state){
                 .source_format = translate_rt_format(rt_resource->base.format, false),
                 .source_tiling = rt_resource->layout,
                 .source_addr = etna_bo_gpu_address(rt_resource->bo) + rt_resource->levels[level].offset,
diff --git a/src/driver/etna_surface.c b/src/driver/etna_surface.c
index 6b07d40..2442758 100644
--- a/src/driver/etna_surface.c
+++ b/src/driver/etna_surface.c
@@ -89,7 +89,7 @@ static struct pipe_surface *etna_pipe_create_surface(struct pipe_context *pipe,
            Currently uses a fixed row size of 64 bytes. Some benchmarking with different sizes may be in order.
          */
         struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
-        etna_compile_rs_state(&surf->clear_command, &(struct rs_state){
+        etna_compile_rs_state(priv->ctx, &surf->clear_command, &(struct rs_state){
                 .source_format = RS_FORMAT_A8R8G8B8,
                 .dest_format = RS_FORMAT_A8R8G8B8,
                 .dest_addr = etna_bo_gpu_address(ts_bo) + surf->surf.ts_offset,
@@ -103,7 +103,7 @@ static struct pipe_surface *etna_pipe_create_surface(struct pipe_context *pipe,
                 .clear_bits = 0xffff
             });
     } else {
-        etna_rs_gen_clear_surface(&surf->clear_command, surf, surf->level->clear_value);
+        etna_rs_gen_clear_surface(priv->ctx, &surf->clear_command, surf, surf->level->clear_value);
     }
     etna_resource_touch(pipe, surf->base.texture);
     return &surf->base;
diff --git a/src/etnaviv/etna_rs.c b/src/etnaviv/etna_rs.c
index 04103ef..873bd59 100644
--- a/src/etnaviv/etna_rs.c
+++ b/src/etnaviv/etna_rs.c
@@ -52,7 +52,7 @@ void etna_warm_up_rs(struct etna_ctx *cmdbuf, viv_addr_t aux_rt_physical, viv_ad
 #define SET_STATE(addr, value) cs->addr = (value)
 #define SET_STATE_FIXP(addr, value) cs->addr = (value)
 #define SET_STATE_F32(addr, value) cs->addr = f32_to_u32(value)
-void etna_compile_rs_state(struct compiled_rs_state *cs, const struct rs_state *rs)
+void etna_compile_rs_state(struct etna_ctx *restrict ctx, struct compiled_rs_state *cs, const struct rs_state *rs)
 {
     /* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */
     unsigned source_stride_shift = (rs->source_tiling != ETNA_LAYOUT_LINEAR) ? 2 : 0;
@@ -74,7 +74,16 @@ void etna_compile_rs_state(struct compiled_rs_state *cs, const struct rs_state *
     SET_STATE(RS_PIPE_DEST_ADDR[0], rs->dest_addr);
     SET_STATE(RS_PIPE_DEST_ADDR[1], rs->dest_addr);  /* TODO */
     SET_STATE(RS_DEST_STRIDE, (rs->dest_stride << dest_stride_shift) | ((rs->dest_tiling&2)?VIVS_RS_DEST_STRIDE_TILING:0));
-    SET_STATE(RS_WINDOW_SIZE, VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) | VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height));
+    if (ctx->conn->chip.pixel_pipes == 1)
+    {
+        SET_STATE(RS_WINDOW_SIZE, VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) | VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height));
+    }
+    else if (ctx->conn->chip.pixel_pipes == 2)
+    {
+        SET_STATE(RS_WINDOW_SIZE, VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) | VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2));
+    }
+    SET_STATE(RS_PIPE_OFFSET[0], VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(0));
+    SET_STATE(RS_PIPE_OFFSET[1], VIVS_RS_PIPE_OFFSET_X(rs->width) | VIVS_RS_PIPE_OFFSET_Y(rs->height / 2));
     SET_STATE(RS_DITHER[0], rs->dither[0]);
     SET_STATE(RS_DITHER[1], rs->dither[1]);
     SET_STATE(RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_BITS(rs->clear_bits) | rs->clear_mode);
diff --git a/src/etnaviv/etna_rs.h b/src/etnaviv/etna_rs.h
index 3593548..b660a10 100644
--- a/src/etnaviv/etna_rs.h
+++ b/src/etnaviv/etna_rs.h
@@ -72,7 +72,7 @@ struct compiled_rs_state
 void etna_warm_up_rs(struct etna_ctx *cmdbuf, viv_addr_t aux_rt_physical, viv_addr_t aux_rt_ts_physical);
 
 /* compile RS state struct */
-void etna_compile_rs_state(struct compiled_rs_state *cs, const struct rs_state *rs);
+void etna_compile_rs_state(struct etna_ctx *restrict ctx, struct compiled_rs_state *cs, const struct rs_state *rs);
 
 /* submit compiled RS state */
 void etna_submit_rs_state(struct etna_ctx *restrict ctx, const struct compiled_rs_state *cs);
diff --git a/src/lib/fbdemos.c b/src/lib/fbdemos.c
index 8763ef4..ed2a384 100644
--- a/src/lib/fbdemos.c
+++ b/src/lib/fbdemos.c
@@ -280,6 +280,7 @@ int fb_close(struct fb_info *fb)
 int etna_fb_bind_resource(struct fb_info *fb, struct pipe_resource *rt_resource_)
 {
     struct etna_resource *rt_resource = etna_resource(rt_resource_);
+    struct etna_pipe_context *ectx = rt_resource->last_ctx;
     fb->resource = rt_resource;
     assert(rt_resource->base.width0 <= fb->fb_var.xres && rt_resource->base.height0 <= fb->fb_var.yres);
     int msaa_xscale=1, msaa_yscale=1;
@@ -288,7 +289,7 @@ int etna_fb_bind_resource(struct fb_info *fb, struct pipe_resource *rt_resource_
 
     for(int bi=0; bi<ETNA_FB_MAX_BUFFERS; ++bi)
     {
-        etna_compile_rs_state(&fb->copy_to_screen[bi], &(struct rs_state){
+        etna_compile_rs_state(ectx->ctx, &fb->copy_to_screen[bi], &(struct rs_state){
                     .source_format = translate_rt_format(rt_resource->base.format, false),
                     .source_tiling = rt_resource->layout,
                     .source_addr = etna_bo_gpu_address(rt_resource->bo) + rt_resource->levels[0].offset,