diff options
| author | Wladimir J. van der Laan <laanwj@gmail.com> | 2014-03-03 16:05:01 +0100 |
|---|---|---|
| committer | Wladimir J. van der Laan <laanwj@gmail.com> | 2014-03-03 17:37:48 +0100 |
| commit | 676ff58bc32134fd26b4c59629f3bcdad1696a45 (patch) | |
| tree | cd8e5a9b9945521e793efd97dab12dc9149ef3ac /src | |
| parent | 35e3d6f80acd729b4b69014f90eb2d3bbc39e99e (diff) | |
driver: fix rendering to texture levels>0 on pre-GC2000
Revert behavior in case of one pixel pipe.
Diffstat (limited to 'src')
| -rw-r--r-- | src/driver/etna_pipe.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/driver/etna_pipe.c b/src/driver/etna_pipe.c index 216b86f..cd377c0 100644 --- a/src/driver/etna_pipe.c +++ b/src/driver/etna_pipe.c @@ -979,9 +979,10 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe, } struct etna_resource *res = etna_resource(cbuf->base.texture); + struct etna_bo *bo = res->bo; if (priv->ctx->conn->chip.pixel_pipes == 1) { - cs->PE_COLOR_ADDR = res->pipe_addr[0]; + cs->PE_COLOR_ADDR = etna_bo_gpu_address(bo) + cbuf->surf.offset; } else if (priv->ctx->conn->chip.pixel_pipes == 2) { @@ -995,7 +996,7 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe, ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR; cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value; cs->TS_COLOR_STATUS_BASE = etna_bo_gpu_address(ts_bo) + cbuf->surf.ts_offset; - cs->TS_COLOR_SURFACE_BASE = res->pipe_addr[0]; + cs->TS_COLOR_SURFACE_BASE = etna_bo_gpu_address(bo) + cbuf->surf.offset; } /* MSAA */ if(cbuf->base.texture->nr_samples > 1) @@ -1021,9 +1022,10 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe, /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */ /* merged with depth_stencil_alpha */ struct etna_resource *res = etna_resource(zsbuf->base.texture); + struct etna_bo *bo = res->bo; if (priv->ctx->conn->chip.pixel_pipes == 1) { - cs->PE_DEPTH_ADDR = res->pipe_addr[0]; + cs->PE_DEPTH_ADDR = etna_bo_gpu_address(bo) + zsbuf->surf.offset; } else if (priv->ctx->conn->chip.pixel_pipes == 2) { @@ -1039,7 +1041,7 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe, ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR; cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value; cs->TS_DEPTH_STATUS_BASE = etna_bo_gpu_address(ts_bo) + zsbuf->surf.ts_offset; - cs->TS_DEPTH_SURFACE_BASE = res->pipe_addr[0]; + cs->TS_DEPTH_SURFACE_BASE = etna_bo_gpu_address(bo) + zsbuf->surf.offset; } ts_mem_config |= (depth_bits == 16 ? VIVS_TS_MEM_CONFIG_DEPTH_16BPP : 0); /* MSAA */ |