summaryrefslogtreecommitdiff
path: root/tools
diff options
context:
space:
mode:
authorWladimir J. van der Laan <laanwj@gmail.com>2013-03-10 10:30:35 +0100
committerWladimir J. van der Laan <laanwj@gmail.com>2013-03-10 10:30:35 +0100
commit4a2b97f85819850ea412c159fded10c9ec9bac56 (patch)
treea389d58cd65ce029963f91a5c18221dc235513eb /tools
parente5d036ada615a2cf144786befef9dda1e6319dd3 (diff)
figure out opcode bit 6, misc fixes and cleanups
- split off x11 based esXXX functions into esWindow, to not cause compilation issues in fb demos on non-X11 Linux hw - add some documentation and comments here and there - define M_PI if needed (I've always believed this to be part of the C standard, it's not!) - figure out some OpenCL instructions, and the extra opcode bit on GC2000 (support it in asm.py / disasm.py)
Diffstat (limited to 'tools')
-rwxr-xr-xtools/asm.py3
-rwxr-xr-xtools/disasm.py2
-rw-r--r--tools/etnaviv/asm_common.py4
3 files changed, 5 insertions, 4 deletions
diff --git a/tools/asm.py b/tools/asm.py
index df42a85..9f815b8 100755
--- a/tools/asm.py
+++ b/tools/asm.py
@@ -61,7 +61,8 @@ def parse_swiz(swiz):
def assemble(isa, inst, warnings):
fields = {}
- fields['OPCODE'] = inst.op
+ fields['OPCODE'] = inst.op & 0x3F
+ fields['OPCODE_BIT6'] = (inst.op >> 6) & 0x01
fields['COND'] = inst.cond
fields['SAT'] = inst.sat
diff --git a/tools/disasm.py b/tools/disasm.py
index dc9b107..565c98e 100755
--- a/tools/disasm.py
+++ b/tools/disasm.py
@@ -43,7 +43,7 @@ def parse_arguments():
help='Binary shader file')
parser.add_argument('-a', dest='addr',
default=False, action='store_const', const=True,
- help='Show address data with instructions')
+ help='Show address with instructions')
parser.add_argument('-r', dest='raw',
default=False, action='store_const', const=True,
help='Show raw data with instructions')
diff --git a/tools/etnaviv/asm_common.py b/tools/etnaviv/asm_common.py
index 1c52a6c..372c05a 100644
--- a/tools/etnaviv/asm_common.py
+++ b/tools/etnaviv/asm_common.py
@@ -67,7 +67,7 @@ def disassemble(isa, inst, warnings):
mask |= field.mask
if mask != 0xffffffff:
warnings.append('isa for word %i incomplete' % word)
- op = fields['OPCODE']
+ op = fields['OPCODE'] | (fields['OPCODE_BIT6'] << 6)
if op in [0x0A, 0x0B]: # Move to address register
dst = DstOperandAReg(
@@ -126,7 +126,7 @@ def disassemble(isa, inst, warnings):
# Unknown fields -- will warn if these are not 0
unknowns = [
- ('bit_1_21', fields['UNK1_21']), ('bit_2_16', fields['UNK2_16']),
+ ('bit_1_21', fields['UNK1_21']),
('bit_2_30', fields['UNK2_30']), ('bit_3_24', fields['UNK3_24']),
('bit_3_31', fields['UNK3_31'])
]