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-rw-r--r--doc/hardware.md24
-rw-r--r--native/fb/Makefile15
-rw-r--r--native/fb/cube_companion.c2
-rw-r--r--native/fb/etna_test.c2
-rw-r--r--native/fb/minigallium.h716
-rw-r--r--native/fb/mip_cube.c33
-rw-r--r--native/fb/mip_cube_state.c570
-rw-r--r--native/fb/rotate_cube.c2
-rw-r--r--native/include/etna/cmdstream.xml.h2
-rw-r--r--native/include/etna/common.xml.h6
-rw-r--r--native/include/etna/state.xml.h6
-rw-r--r--native/include/etna/state_2d.xml.h6
-rw-r--r--native/include/etna/state_3d.xml.h47
-rw-r--r--native/include/etna/state_hi.xml.h6
-rw-r--r--native/lib/etna_context_cmd.h4
-rw-r--r--native/lib/etna_tex.c36
-rw-r--r--native/lib/etna_tex.h6
-rw-r--r--native/replay/Makefile5
-rw-r--r--native/replay/cube_etna.c2
-rw-r--r--native/replay/cube_etna2.c2
-rw-r--r--native/replay/etna_test.c2
-rw-r--r--native/replay/ps_sandbox_etna.c2
-rw-r--r--rnndb/common.xml260
-rw-r--r--rnndb/state.xml2
-rw-r--r--rnndb/state_3d.xml821
25 files changed, 2452 insertions, 127 deletions
diff --git a/doc/hardware.md b/doc/hardware.md
index 8d9c508..fd67c97 100644
--- a/doc/hardware.md
+++ b/doc/hardware.md
@@ -1,28 +1,32 @@
GCxxx hardware
===============
-Major optional blocks. Each of these can be present or not depending on the specific chip:
+Major optional blocks: each of these can be present or not depending on the specific chip:
- 2D engine
-- Composition engine (multi source blit)
+- Composition engine
- 3D engine
- VG engine
+Some SoCs have multiple GPU cores, and have distributed these blocks over the cores (I suppose for extra parallelism and/or
+granularity in power switching). For example the Marvell Armada 620 has a GC2000 with only the 3D engine as well
+as a GC300 with only the 2D engine.
+
Feature bits
=================
-Variants are somewhat different from NV; what features are supported is not so much determined by the model number
-(which mainly determines the performance), but determined by various properties that can be found in
-read-only registers in the hardware:
+Which features are supported on a certain Vivante core is not only determined by the model number
+(which AFAIK mainly determines the performance), but determined by a combination of feature bits:
1) Chip features and minor feature flags
2) Chip specs (number of instructions, pipelines, ...)
3) Chip model (GC800, GC2000, ...)
4) Chip revision of the form 0x1234
-Generally the chip feature flags are used to distinguish functionality, as well as the specs, and not do much the model
-and revision. Unlike NV, which parametrizes everything on the model and revision, for GC this is left for bugfixes
-(but even these sometimes have their own feature bit).
+All of these are available in read-only registers on the hardware. On most cases it suffices to check the feature flags.
+
+Unlike NV, which parametrizes everything on the model and revision, for GC this is left for bugfixes (but
+even these sometimes have their own feature bit).
For an overview of the feature bits see the enumerations in `state.xml`.
@@ -90,7 +94,7 @@ Thread walker = Rectangle walker? (seems to have to do with OpenCL)
Connections
-------------
-Follows the OpenGL pipeline design [3].
+Connections between the different module follow the OpenGL pipeline design [3].
- FE2VS (FE-VS) fetch engine to vertex shader: attributes
- RA2SH (RA-PS) rasterizer to shader engine: varyings
@@ -100,7 +104,7 @@ Overall:
FE -> VS -> PA -> SE -> RA -> PS -> PE -> RS
-How does PA/SE fit in this picture? Connection seems to be VS -> PA -> SE -> RA [1]
+See also [1]
- PA assembles 3D primitives from vertices, culls based on trivial rejection and clips based on near Z-plane
- PA transforms from 3D view frustum into 2D screen space
diff --git a/native/fb/Makefile b/native/fb/Makefile
index f8d17a8..967088b 100644
--- a/native/fb/Makefile
+++ b/native/fb/Makefile
@@ -9,6 +9,7 @@ LDFLAGS += -lm
TARGETS = fbtest etna_test rotate_cube cube_companion mip_cube rstests mip_cube_state
COMPANION_OBJS = ../resources/companion_array.o ../resources/companion_mesh.o ../resources/companion_texture.o
+ETNA_OBJS = ../lib/viv.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_fb.o ../lib/etna_mem.o ../lib/etna_bswap.o ../lib/etna_tex.o
all: $(TARGETS)
@@ -16,24 +17,24 @@ clean:
rm -f *.o ../lib/*.o
rm -f $(TARGETS)
-fbtest: fbtest.o ../lib/write_bmp.o ../lib/viv.o ../lib/etna_fb.o
+fbtest: fbtest.o ../lib/write_bmp.o $(ETNA_OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
-etna_test: etna_test.o ../lib/write_bmp.o ../lib/viv.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_fb.o ../lib/etna_mem.o
+etna_test: etna_test.o ../lib/write_bmp.o $(ETNA_OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
-rotate_cube: rotate_cube.o ../lib/write_bmp.o ../lib/viv.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_fb.o ../lib/etna_mem.o ../lib/esTransform.o
+rotate_cube: rotate_cube.o ../lib/write_bmp.o $(ETNA_OBJS) ../lib/esTransform.o
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
-mip_cube: mip_cube.o ../lib/write_bmp.o ../lib/viv.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_fb.o ../lib/etna_mem.o ../lib/esTransform.o ../lib/dds.o ../lib/etna_bswap.o
+mip_cube: mip_cube.o ../lib/write_bmp.o ../lib/esTransform.o ../lib/dds.o $(ETNA_OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
-mip_cube_state: mip_cube_state.o ../lib/write_bmp.o ../lib/viv.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_fb.o ../lib/etna_mem.o ../lib/esTransform.o ../lib/dds.o ../lib/etna_bswap.o
+mip_cube_state: mip_cube_state.o ../lib/write_bmp.o ../lib/esTransform.o ../lib/dds.o $(ETNA_OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
-cube_companion: cube_companion.o ../lib/write_bmp.o ../lib/viv.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_fb.o ../lib/etna_mem.o ../lib/esTransform.o $(COMPANION_OBJS)
+cube_companion: cube_companion.o ../lib/write_bmp.o ../lib/esTransform.o $(COMPANION_OBJS) $(ETNA_OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
-rstests: rstests.o ../lib/write_bmp.o ../lib/viv.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_fb.o ../lib/etna_mem.o ../lib/esTransform.o $(COMPANION_OBJS)
+rstests: rstests.o ../lib/write_bmp.o ../lib/esTransform.o $(COMPANION_OBJS) $(ETNA_OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
diff --git a/native/fb/cube_companion.c b/native/fb/cube_companion.c
index 935cd73..34238dc 100644
--- a/native/fb/cube_companion.c
+++ b/native/fb/cube_companion.c
@@ -279,7 +279,7 @@ int main(int argc, char **argv)
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
- ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) &
+ ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
diff --git a/native/fb/etna_test.c b/native/fb/etna_test.c
index 430d3e0..43a5250 100644
--- a/native/fb/etna_test.c
+++ b/native/fb/etna_test.c
@@ -191,7 +191,7 @@ int main(int argc, char **argv)
/* Set up pixel engine */
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
- ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) &
+ ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
diff --git a/native/fb/minigallium.h b/native/fb/minigallium.h
new file mode 100644
index 0000000..0e7058c
--- /dev/null
+++ b/native/fb/minigallium.h
@@ -0,0 +1,716 @@
+/**************************************************************************
+ *
+ * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2009-2010 VMware, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+#ifndef H_MINIGALLIUM
+#define H_MINIGALLIUM
+/********************************************************************
+ * State and tokens from gallium, for experimentation
+ *******************************************************************/
+
+union pipe_color_union
+{
+ float f[4];
+ int i[4];
+ unsigned int ui[4];
+};
+
+#define PIPE_BLENDFACTOR_ONE 0x1
+#define PIPE_BLENDFACTOR_SRC_COLOR 0x2
+#define PIPE_BLENDFACTOR_SRC_ALPHA 0x3
+#define PIPE_BLENDFACTOR_DST_ALPHA 0x4
+#define PIPE_BLENDFACTOR_DST_COLOR 0x5
+#define PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6
+#define PIPE_BLENDFACTOR_CONST_COLOR 0x7
+#define PIPE_BLENDFACTOR_CONST_ALPHA 0x8
+#define PIPE_BLENDFACTOR_SRC1_COLOR 0x9
+#define PIPE_BLENDFACTOR_SRC1_ALPHA 0x0A
+#define PIPE_BLENDFACTOR_ZERO 0x11
+#define PIPE_BLENDFACTOR_INV_SRC_COLOR 0x12
+#define PIPE_BLENDFACTOR_INV_SRC_ALPHA 0x13
+#define PIPE_BLENDFACTOR_INV_DST_ALPHA 0x14
+#define PIPE_BLENDFACTOR_INV_DST_COLOR 0x15
+#define PIPE_BLENDFACTOR_INV_CONST_COLOR 0x17
+#define PIPE_BLENDFACTOR_INV_CONST_ALPHA 0x18
+#define PIPE_BLENDFACTOR_INV_SRC1_COLOR 0x19
+#define PIPE_BLENDFACTOR_INV_SRC1_ALPHA 0x1A
+
+#define PIPE_BLEND_ADD 0
+#define PIPE_BLEND_SUBTRACT 1
+#define PIPE_BLEND_REVERSE_SUBTRACT 2
+#define PIPE_BLEND_MIN 3
+#define PIPE_BLEND_MAX 4
+/**
+ * Primitive (point/line/tri) rasterization info
+ */
+#define PIPE_MAX_ATTRIBS 32
+#define PIPE_MAX_CLIP_PLANES 8
+#define PIPE_MAX_COLOR_BUFS 8
+#define PIPE_MAX_CONSTANT_BUFFERS 32
+#define PIPE_MAX_SAMPLERS 16
+#define PIPE_MAX_SHADER_INPUTS 32
+#define PIPE_MAX_SHADER_OUTPUTS 48 /* 32 GENERICs + POS, PSIZE, FOG, etc. */
+#define PIPE_MAX_SHADER_SAMPLER_VIEWS 32
+#define PIPE_MAX_SHADER_RESOURCES 32
+#define PIPE_MAX_TEXTURE_LEVELS 16
+#define PIPE_MAX_SO_BUFFERS 4
+
+/** Polygon fill mode */
+#define PIPE_FACE_NONE 0
+#define PIPE_FACE_FRONT 1
+#define PIPE_FACE_BACK 2
+#define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
+
+/** Polygon fill mode */
+#define PIPE_POLYGON_MODE_FILL 0
+#define PIPE_POLYGON_MODE_LINE 1
+#define PIPE_POLYGON_MODE_POINT 2
+
+/**
+ * Inequality functions. Used for depth test, stencil compare, alpha
+ * test, shadow compare, etc.
+ */
+#define PIPE_FUNC_NEVER 0
+#define PIPE_FUNC_LESS 1
+#define PIPE_FUNC_EQUAL 2
+#define PIPE_FUNC_LEQUAL 3
+#define PIPE_FUNC_GREATER 4
+#define PIPE_FUNC_NOTEQUAL 5
+#define PIPE_FUNC_GEQUAL 6
+#define PIPE_FUNC_ALWAYS 7
+
+/** Stencil ops */
+#define PIPE_STENCIL_OP_KEEP 0
+#define PIPE_STENCIL_OP_ZERO 1
+#define PIPE_STENCIL_OP_REPLACE 2
+#define PIPE_STENCIL_OP_INCR 3
+#define PIPE_STENCIL_OP_DECR 4
+#define PIPE_STENCIL_OP_INCR_WRAP 5
+#define PIPE_STENCIL_OP_DECR_WRAP 6
+#define PIPE_STENCIL_OP_INVERT 7
+
+/** Texture types.
+ * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D */
+enum pipe_texture_target {
+ PIPE_BUFFER = 0,
+ PIPE_TEXTURE_1D = 1,
+ PIPE_TEXTURE_2D = 2,
+ PIPE_TEXTURE_3D = 3,
+ PIPE_TEXTURE_CUBE = 4,
+ PIPE_TEXTURE_RECT = 5,
+ PIPE_TEXTURE_1D_ARRAY = 6,
+ PIPE_TEXTURE_2D_ARRAY = 7,
+ PIPE_TEXTURE_CUBE_ARRAY = 8,
+ PIPE_MAX_TEXTURE_TYPES
+};
+
+#define PIPE_TEX_WRAP_REPEAT 0
+#define PIPE_TEX_WRAP_CLAMP 1
+#define PIPE_TEX_WRAP_CLAMP_TO_EDGE 2
+#define PIPE_TEX_WRAP_CLAMP_TO_BORDER 3
+#define PIPE_TEX_WRAP_MIRROR_REPEAT 4
+#define PIPE_TEX_WRAP_MIRROR_CLAMP 5
+#define PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE 6
+#define PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER 7
+
+/* Between mipmaps, ie mipfilter
+ */
+#define PIPE_TEX_MIPFILTER_NEAREST 0
+#define PIPE_TEX_MIPFILTER_LINEAR 1
+#define PIPE_TEX_MIPFILTER_NONE 2
+
+/* Within a mipmap, ie min/mag filter
+ */
+#define PIPE_TEX_FILTER_NEAREST 0
+#define PIPE_TEX_FILTER_LINEAR 1
+
+#define PIPE_TEX_COMPARE_NONE 0
+#define PIPE_TEX_COMPARE_R_TO_TEXTURE 1
+
+enum pipe_type {
+ PIPE_TYPE_UNORM = 0,
+ PIPE_TYPE_SNORM,
+ PIPE_TYPE_SINT,
+ PIPE_TYPE_UINT,
+ PIPE_TYPE_FLOAT,
+ PIPE_TYPE_COUNT
+};
+
+/**
+ * Texture/surface image formats (preliminary)
+ */
+
+/* KW: Added lots of surface formats to support vertex element layout
+ * definitions, and eventually render-to-vertex-buffer.
+ */
+
+enum pipe_format {
+ PIPE_FORMAT_NONE = 0,
+ PIPE_FORMAT_B8G8R8A8_UNORM = 1,
+ PIPE_FORMAT_B8G8R8X8_UNORM = 2,
+ PIPE_FORMAT_A8R8G8B8_UNORM = 3,
+ PIPE_FORMAT_X8R8G8B8_UNORM = 4,
+ PIPE_FORMAT_B5G5R5A1_UNORM = 5,
+ PIPE_FORMAT_B4G4R4A4_UNORM = 6,
+ PIPE_FORMAT_B5G6R5_UNORM = 7,
+ PIPE_FORMAT_R10G10B10A2_UNORM = 8,
+ PIPE_FORMAT_L8_UNORM = 9, /**< ubyte luminance */
+ PIPE_FORMAT_A8_UNORM = 10, /**< ubyte alpha */
+ PIPE_FORMAT_I8_UNORM = 11, /**< ubyte intensity */
+ PIPE_FORMAT_L8A8_UNORM = 12, /**< ubyte alpha, luminance */
+ PIPE_FORMAT_L16_UNORM = 13, /**< ushort luminance */
+ PIPE_FORMAT_UYVY = 14,
+ PIPE_FORMAT_YUYV = 15,
+ PIPE_FORMAT_Z16_UNORM = 16,
+ PIPE_FORMAT_Z32_UNORM = 17,
+ PIPE_FORMAT_Z32_FLOAT = 18,
+ PIPE_FORMAT_Z24_UNORM_S8_UINT = 19,
+ PIPE_FORMAT_S8_UINT_Z24_UNORM = 20,
+ PIPE_FORMAT_Z24X8_UNORM = 21,
+ PIPE_FORMAT_X8Z24_UNORM = 22,
+ PIPE_FORMAT_S8_UINT = 23, /**< ubyte stencil */
+ PIPE_FORMAT_R64_FLOAT = 24,
+ PIPE_FORMAT_R64G64_FLOAT = 25,
+ PIPE_FORMAT_R64G64B64_FLOAT = 26,
+ PIPE_FORMAT_R64G64B64A64_FLOAT = 27,
+ PIPE_FORMAT_R32_FLOAT = 28,
+ PIPE_FORMAT_R32G32_FLOAT = 29,
+ PIPE_FORMAT_R32G32B32_FLOAT = 30,
+ PIPE_FORMAT_R32G32B32A32_FLOAT = 31,
+ PIPE_FORMAT_R32_UNORM = 32,
+ PIPE_FORMAT_R32G32_UNORM = 33,
+ PIPE_FORMAT_R32G32B32_UNORM = 34,
+ PIPE_FORMAT_R32G32B32A32_UNORM = 35,
+ PIPE_FORMAT_R32_USCALED = 36,
+ PIPE_FORMAT_R32G32_USCALED = 37,
+ PIPE_FORMAT_R32G32B32_USCALED = 38,
+ PIPE_FORMAT_R32G32B32A32_USCALED = 39,
+ PIPE_FORMAT_R32_SNORM = 40,
+ PIPE_FORMAT_R32G32_SNORM = 41,
+ PIPE_FORMAT_R32G32B32_SNORM = 42,
+ PIPE_FORMAT_R32G32B32A32_SNORM = 43,
+ PIPE_FORMAT_R32_SSCALED = 44,
+ PIPE_FORMAT_R32G32_SSCALED = 45,
+ PIPE_FORMAT_R32G32B32_SSCALED = 46,
+ PIPE_FORMAT_R32G32B32A32_SSCALED = 47,
+ PIPE_FORMAT_R16_UNORM = 48,
+ PIPE_FORMAT_R16G16_UNORM = 49,
+ PIPE_FORMAT_R16G16B16_UNORM = 50,
+ PIPE_FORMAT_R16G16B16A16_UNORM = 51,
+ PIPE_FORMAT_R16_USCALED = 52,
+ PIPE_FORMAT_R16G16_USCALED = 53,
+ PIPE_FORMAT_R16G16B16_USCALED = 54,
+ PIPE_FORMAT_R16G16B16A16_USCALED = 55,
+ PIPE_FORMAT_R16_SNORM = 56,
+ PIPE_FORMAT_R16G16_SNORM = 57,
+ PIPE_FORMAT_R16G16B16_SNORM = 58,
+ PIPE_FORMAT_R16G16B16A16_SNORM = 59,
+ PIPE_FORMAT_R16_SSCALED = 60,
+ PIPE_FORMAT_R16G16_SSCALED = 61,
+ PIPE_FORMAT_R16G16B16_SSCALED = 62,
+ PIPE_FORMAT_R16G16B16A16_SSCALED = 63,
+ PIPE_FORMAT_R8_UNORM = 64,
+ PIPE_FORMAT_R8G8_UNORM = 65,
+ PIPE_FORMAT_R8G8B8_UNORM = 66,
+ PIPE_FORMAT_R8G8B8A8_UNORM = 67,
+ PIPE_FORMAT_X8B8G8R8_UNORM = 68,
+ PIPE_FORMAT_R8_USCALED = 69,
+ PIPE_FORMAT_R8G8_USCALED = 70,
+ PIPE_FORMAT_R8G8B8_USCALED = 71,
+ PIPE_FORMAT_R8G8B8A8_USCALED = 72,
+ PIPE_FORMAT_R8_SNORM = 74,
+ PIPE_FORMAT_R8G8_SNORM = 75,
+ PIPE_FORMAT_R8G8B8_SNORM = 76,
+ PIPE_FORMAT_R8G8B8A8_SNORM = 77,
+ PIPE_FORMAT_R8_SSCALED = 82,
+ PIPE_FORMAT_R8G8_SSCALED = 83,
+ PIPE_FORMAT_R8G8B8_SSCALED = 84,
+ PIPE_FORMAT_R8G8B8A8_SSCALED = 85,
+ PIPE_FORMAT_R32_FIXED = 87,
+ PIPE_FORMAT_R32G32_FIXED = 88,
+ PIPE_FORMAT_R32G32B32_FIXED = 89,
+ PIPE_FORMAT_R32G32B32A32_FIXED = 90,
+ PIPE_FORMAT_R16_FLOAT = 91,
+ PIPE_FORMAT_R16G16_FLOAT = 92,
+ PIPE_FORMAT_R16G16B16_FLOAT = 93,
+ PIPE_FORMAT_R16G16B16A16_FLOAT = 94,
+
+ /* sRGB formats */
+ PIPE_FORMAT_L8_SRGB = 95,
+ PIPE_FORMAT_L8A8_SRGB = 96,
+ PIPE_FORMAT_R8G8B8_SRGB = 97,
+ PIPE_FORMAT_A8B8G8R8_SRGB = 98,
+ PIPE_FORMAT_X8B8G8R8_SRGB = 99,
+ PIPE_FORMAT_B8G8R8A8_SRGB = 100,
+ PIPE_FORMAT_B8G8R8X8_SRGB = 101,
+ PIPE_FORMAT_A8R8G8B8_SRGB = 102,
+ PIPE_FORMAT_X8R8G8B8_SRGB = 103,
+ PIPE_FORMAT_R8G8B8A8_SRGB = 104,
+
+ /* compressed formats */
+ PIPE_FORMAT_DXT1_RGB = 105,
+ PIPE_FORMAT_DXT1_RGBA = 106,
+ PIPE_FORMAT_DXT3_RGBA = 107,
+ PIPE_FORMAT_DXT5_RGBA = 108,
+
+ /* sRGB, compressed */
+ PIPE_FORMAT_DXT1_SRGB = 109,
+ PIPE_FORMAT_DXT1_SRGBA = 110,
+ PIPE_FORMAT_DXT3_SRGBA = 111,
+ PIPE_FORMAT_DXT5_SRGBA = 112,
+
+ /* rgtc compressed */
+ PIPE_FORMAT_RGTC1_UNORM = 113,
+ PIPE_FORMAT_RGTC1_SNORM = 114,
+ PIPE_FORMAT_RGTC2_UNORM = 115,
+ PIPE_FORMAT_RGTC2_SNORM = 116,
+
+ PIPE_FORMAT_R8G8_B8G8_UNORM = 117,
+ PIPE_FORMAT_G8R8_G8B8_UNORM = 118,
+
+ /* mixed formats */
+ PIPE_FORMAT_R8SG8SB8UX8U_NORM = 119,
+ PIPE_FORMAT_R5SG5SB6U_NORM = 120,
+
+ /* TODO: re-order these */
+ PIPE_FORMAT_A8B8G8R8_UNORM = 121,
+ PIPE_FORMAT_B5G5R5X1_UNORM = 122,
+ PIPE_FORMAT_R10G10B10A2_USCALED = 123,
+ PIPE_FORMAT_R11G11B10_FLOAT = 124,
+ PIPE_FORMAT_R9G9B9E5_FLOAT = 125,
+ PIPE_FORMAT_Z32_FLOAT_S8X24_UINT = 126,
+ PIPE_FORMAT_R1_UNORM = 127,
+ PIPE_FORMAT_R10G10B10X2_USCALED = 128,
+ PIPE_FORMAT_R10G10B10X2_SNORM = 129,
+ PIPE_FORMAT_L4A4_UNORM = 130,
+ PIPE_FORMAT_B10G10R10A2_UNORM = 131,
+ PIPE_FORMAT_R10SG10SB10SA2U_NORM = 132,
+ PIPE_FORMAT_R8G8Bx_SNORM = 133,
+ PIPE_FORMAT_R8G8B8X8_UNORM = 134,
+ PIPE_FORMAT_B4G4R4X4_UNORM = 135,
+
+ /* some stencil samplers formats */
+ PIPE_FORMAT_X24S8_UINT = 136,
+ PIPE_FORMAT_S8X24_UINT = 137,
+ PIPE_FORMAT_X32_S8X24_UINT = 138,
+
+ PIPE_FORMAT_B2G3R3_UNORM = 139,
+ PIPE_FORMAT_L16A16_UNORM = 140,
+ PIPE_FORMAT_A16_UNORM = 141,
+ PIPE_FORMAT_I16_UNORM = 142,
+
+ PIPE_FORMAT_LATC1_UNORM = 143,
+ PIPE_FORMAT_LATC1_SNORM = 144,
+ PIPE_FORMAT_LATC2_UNORM = 145,
+ PIPE_FORMAT_LATC2_SNORM = 146,
+
+ PIPE_FORMAT_A8_SNORM = 147,
+ PIPE_FORMAT_L8_SNORM = 148,
+ PIPE_FORMAT_L8A8_SNORM = 149,
+ PIPE_FORMAT_I8_SNORM = 150,
+ PIPE_FORMAT_A16_SNORM = 151,
+ PIPE_FORMAT_L16_SNORM = 152,
+ PIPE_FORMAT_L16A16_SNORM = 153,
+ PIPE_FORMAT_I16_SNORM = 154,
+
+ PIPE_FORMAT_A16_FLOAT = 155,
+ PIPE_FORMAT_L16_FLOAT = 156,
+ PIPE_FORMAT_L16A16_FLOAT = 157,
+ PIPE_FORMAT_I16_FLOAT = 158,
+ PIPE_FORMAT_A32_FLOAT = 159,
+ PIPE_FORMAT_L32_FLOAT = 160,
+ PIPE_FORMAT_L32A32_FLOAT = 161,
+ PIPE_FORMAT_I32_FLOAT = 162,
+
+ PIPE_FORMAT_YV12 = 163,
+ PIPE_FORMAT_YV16 = 164,
+ PIPE_FORMAT_IYUV = 165, /**< aka I420 */
+ PIPE_FORMAT_NV12 = 166,
+ PIPE_FORMAT_NV21 = 167,
+
+ PIPE_FORMAT_R4A4_UNORM = 168,
+ PIPE_FORMAT_A4R4_UNORM = 169,
+ PIPE_FORMAT_R8A8_UNORM = 170,
+ PIPE_FORMAT_A8R8_UNORM = 171,
+
+ PIPE_FORMAT_R10G10B10A2_SSCALED = 172,
+ PIPE_FORMAT_R10G10B10A2_SNORM = 173,
+
+ PIPE_FORMAT_B10G10R10A2_USCALED = 174,
+ PIPE_FORMAT_B10G10R10A2_SSCALED = 175,
+ PIPE_FORMAT_B10G10R10A2_SNORM = 176,
+
+ PIPE_FORMAT_R8_UINT = 177,
+ PIPE_FORMAT_R8G8_UINT = 178,
+ PIPE_FORMAT_R8G8B8_UINT = 179,
+ PIPE_FORMAT_R8G8B8A8_UINT = 180,
+
+ PIPE_FORMAT_R8_SINT = 181,
+ PIPE_FORMAT_R8G8_SINT = 182,
+ PIPE_FORMAT_R8G8B8_SINT = 183,
+ PIPE_FORMAT_R8G8B8A8_SINT = 184,
+
+ PIPE_FORMAT_R16_UINT = 185,
+ PIPE_FORMAT_R16G16_UINT = 186,
+ PIPE_FORMAT_R16G16B16_UINT = 187,
+ PIPE_FORMAT_R16G16B16A16_UINT = 188,
+
+ PIPE_FORMAT_R16_SINT = 189,
+ PIPE_FORMAT_R16G16_SINT = 190,
+ PIPE_FORMAT_R16G16B16_SINT = 191,
+ PIPE_FORMAT_R16G16B16A16_SINT = 192,
+
+ PIPE_FORMAT_R32_UINT = 193,
+ PIPE_FORMAT_R32G32_UINT = 194,
+ PIPE_FORMAT_R32G32B32_UINT = 195,
+ PIPE_FORMAT_R32G32B32A32_UINT = 196,
+
+ PIPE_FORMAT_R32_SINT = 197,
+ PIPE_FORMAT_R32G32_SINT = 198,
+ PIPE_FORMAT_R32G32B32_SINT = 199,
+ PIPE_FORMAT_R32G32B32A32_SINT = 200,
+
+ PIPE_FORMAT_A8_UINT = 201,
+ PIPE_FORMAT_I8_UINT = 202,
+ PIPE_FORMAT_L8_UINT = 203,
+ PIPE_FORMAT_L8A8_UINT = 204,
+
+ PIPE_FORMAT_A8_SINT = 205,
+ PIPE_FORMAT_I8_SINT = 206,
+ PIPE_FORMAT_L8_SINT = 207,
+ PIPE_FORMAT_L8A8_SINT = 208,
+
+ PIPE_FORMAT_A16_UINT = 209,
+ PIPE_FORMAT_I16_UINT = 210,
+ PIPE_FORMAT_L16_UINT = 211,
+ PIPE_FORMAT_L16A16_UINT = 212,
+
+ PIPE_FORMAT_A16_SINT = 213,
+ PIPE_FORMAT_I16_SINT = 214,
+ PIPE_FORMAT_L16_SINT = 215,
+ PIPE_FORMAT_L16A16_SINT = 216,
+
+ PIPE_FORMAT_A32_UINT = 217,
+ PIPE_FORMAT_I32_UINT = 218,
+ PIPE_FORMAT_L32_UINT = 219,
+ PIPE_FORMAT_L32A32_UINT = 220,
+
+ PIPE_FORMAT_A32_SINT = 221,
+ PIPE_FORMAT_I32_SINT = 222,
+ PIPE_FORMAT_L32_SINT = 223,
+ PIPE_FORMAT_L32A32_SINT = 224,
+
+ PIPE_FORMAT_B10G10R10A2_UINT = 225,
+
+ PIPE_FORMAT_ETC1_RGB8 = 226,
+
+ PIPE_FORMAT_R8G8_R8B8_UNORM = 227,
+ PIPE_FORMAT_G8R8_B8R8_UNORM = 228,
+
+ PIPE_FORMAT_COUNT
+};
+
+
+struct pipe_rasterizer_state
+{
+ unsigned flatshade:1;
+ unsigned light_twoside:1;
+ unsigned clamp_vertex_color:1;
+ unsigned clamp_fragment_color:1;
+ unsigned front_ccw:1;
+ unsigned cull_face:2; /**< PIPE_FACE_x */
+ unsigned fill_front:2; /**< PIPE_POLYGON_MODE_x */
+ unsigned fill_back:2; /**< PIPE_POLYGON_MODE_x */
+ unsigned offset_point:1;
+ unsigned offset_line:1;
+ unsigned offset_tri:1;
+ unsigned scissor:1;
+ unsigned poly_smooth:1;
+ unsigned poly_stipple_enable:1;
+ unsigned point_smooth:1;
+ unsigned sprite_coord_mode:1; /**< PIPE_SPRITE_COORD_ */
+ unsigned point_quad_rasterization:1; /** points rasterized as quads or points */
+ unsigned point_size_per_vertex:1; /**< size computed in vertex shader */
+ unsigned multisample:1; /* XXX maybe more ms state in future */
+ unsigned line_smooth:1;
+ unsigned line_stipple_enable:1;
+ unsigned line_last_pixel:1;
+
+ /**
+ * Use the first vertex of a primitive as the provoking vertex for
+ * flat shading.
+ */
+ unsigned flatshade_first:1;
+
+ /**
+ * When true, triangle rasterization uses (0.5, 0.5) pixel centers
+ * for determining pixel ownership.
+ *
+ * When false, triangle rasterization uses (0,0) pixel centers for
+ * determining pixel ownership.
+ *
+ * Triangle rasterization always uses a 'top,left' rule for pixel
+ * ownership, this just alters which point we consider the pixel
+ * center for that test.
+ */
+ unsigned gl_rasterization_rules:1;
+
+ /**
+ * When true, rasterization is disabled and no pixels are written.
+ * This only makes sense with the Stream Out functionality.
+ */
+ unsigned rasterizer_discard:1;
+
+ /**
+ * When false, depth clipping is disabled and the depth value will be
+ * clamped later at the per-pixel level before depth testing.
+ * This depends on PIPE_CAP_DEPTH_CLIP_DISABLE.
+ */
+ unsigned depth_clip:1;
+
+ /**
+ * Enable bits for clipping half-spaces.
+ * This applies to both user clip planes and shader clip distances.
+ * Note that if the bound shader exports any clip distances, these
+ * replace all user clip planes, and clip half-spaces enabled here
+ * but not written by the shader count as disabled.
+ */
+ unsigned clip_plane_enable:PIPE_MAX_CLIP_PLANES;
+
+ unsigned line_stipple_factor:8; /**< [1..256] actually */
+ unsigned line_stipple_pattern:16;
+
+ unsigned sprite_coord_enable; /* bitfield referring to 32 GENERIC inputs */
+
+ float line_width;
+ float point_size; /**< used when no per-vertex size */
+ float offset_units;
+ float offset_scale;
+ float offset_clamp;
+};
+
+struct pipe_viewport_state
+{
+ float scale[4];
+ float translate[4];
+};
+
+
+struct pipe_scissor_state
+{
+ unsigned minx:16;
+ unsigned miny:16;
+ unsigned maxx:16;
+ unsigned maxy:16;
+};
+struct pipe_depth_state
+{
+ unsigned enabled:1; /**< depth test enabled? */
+ unsigned writemask:1; /**< allow depth buffer writes? */
+ unsigned func:3; /**< depth test func (PIPE_FUNC_x) */
+};
+
+
+struct pipe_stencil_state
+{
+ unsigned enabled:1; /**< stencil[0]: stencil enabled, stencil[1]: two-side enabled */
+ unsigned func:3; /**< PIPE_FUNC_x */
+ unsigned fail_op:3; /**< PIPE_STENCIL_OP_x */
+ unsigned zpass_op:3; /**< PIPE_STENCIL_OP_x */
+ unsigned zfail_op:3; /**< PIPE_STENCIL_OP_x */
+ unsigned valuemask:8;
+ unsigned writemask:8;
+};
+
+
+struct pipe_alpha_state
+{
+ unsigned enabled:1;
+ unsigned func:3; /**< PIPE_FUNC_x */
+ float ref_value; /**< reference value */
+};
+
+
+struct pipe_depth_stencil_alpha_state
+{
+ struct pipe_depth_state depth;
+ struct pipe_stencil_state stencil[2]; /**< [0] = front, [1] = back */
+ struct pipe_alpha_state alpha;
+};
+
+
+struct pipe_rt_blend_state
+{
+ unsigned blend_enable:1;
+
+ unsigned rgb_func:3; /**< PIPE_BLEND_x */
+ unsigned rgb_src_factor:5; /**< PIPE_BLENDFACTOR_x */
+ unsigned rgb_dst_factor:5; /**< PIPE_BLENDFACTOR_x */
+
+ unsigned alpha_func:3; /**< PIPE_BLEND_x */
+ unsigned alpha_src_factor:5; /**< PIPE_BLENDFACTOR_x */
+ unsigned alpha_dst_factor:5; /**< PIPE_BLENDFACTOR_x */
+
+ unsigned colormask:4; /**< bitmask of PIPE_MASK_R/G/B/A */
+};
+
+struct pipe_blend_state
+{
+ unsigned independent_blend_enable:1;
+ unsigned logicop_enable:1;
+ unsigned logicop_func:4; /**< PIPE_LOGICOP_x */
+ unsigned dither:1;
+ unsigned alpha_to_coverage:1;
+ unsigned alpha_to_one:1;
+ struct pipe_rt_blend_state rt[PIPE_MAX_COLOR_BUFS];
+};
+
+
+struct pipe_blend_color
+{
+ float color[4];
+};
+
+struct pipe_stencil_ref
+{
+ uint8_t ref_value[2];
+};
+
+struct pipe_framebuffer_state
+{
+ unsigned width, height;
+
+ /** multiple color buffers for multiple render targets */
+ unsigned nr_cbufs;
+ struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS];
+
+ struct pipe_surface *zsbuf; /**< Z/stencil buffer */
+};
+
+/**
+ * Texture sampler state.
+ */
+struct pipe_sampler_state
+{
+ unsigned wrap_s:3; /**< PIPE_TEX_WRAP_x */
+ unsigned wrap_t:3; /**< PIPE_TEX_WRAP_x */
+ unsigned wrap_r:3; /**< PIPE_TEX_WRAP_x */
+ unsigned min_img_filter:2; /**< PIPE_TEX_FILTER_x */
+ unsigned min_mip_filter:2; /**< PIPE_TEX_MIPFILTER_x */
+ unsigned mag_img_filter:2; /**< PIPE_TEX_FILTER_x */
+ unsigned compare_mode:1; /**< PIPE_TEX_COMPARE_x */
+ unsigned compare_func:3; /**< PIPE_FUNC_x */
+ unsigned normalized_coords:1; /**< Are coords normalized to [0,1]? */
+ unsigned max_anisotropy:6;
+ unsigned seamless_cube_map:1;
+ float lod_bias; /**< LOD/lambda bias */
+ float min_lod, max_lod; /**< LOD clamp range, after bias */
+ union pipe_color_union border_color;
+};
+
+/**
+ * A memory object/resource such as a vertex buffer or texture.
+ */
+struct pipe_resource
+{
+ /* struct pipe_reference reference; */
+ struct pipe_screen *screen; /**< screen that this texture belongs to */
+ enum pipe_texture_target target; /**< PIPE_TEXTURE_x */
+ enum pipe_format format; /**< PIPE_FORMAT_x */
+
+ unsigned width0;
+ unsigned height0;
+ unsigned depth0;
+ unsigned array_size;
+
+ unsigned last_level:8; /**< Index of last mipmap level present/defined */
+ unsigned nr_samples:8; /**< for multisampled surfaces, nr of samples */
+ unsigned usage:8; /**< PIPE_USAGE_x (not a bitmask) */
+
+ unsigned bind; /**< bitmask of PIPE_BIND_x */
+ unsigned flags; /**< bitmask of PIPE_RESOURCE_FLAG_x */
+};
+
+/**
+ * A view into a texture that can be bound to a color render target /
+ * depth stencil attachment point.
+ */
+struct pipe_surface
+{
+ /* struct pipe_reference reference; */
+ struct pipe_resource *texture; /**< resource into which this is a view */
+ struct pipe_context *context; /**< context this surface belongs to */
+ enum pipe_format format;
+
+ /* XXX width/height should be removed */
+ unsigned width; /**< logical width in pixels */
+ unsigned height; /**< logical height in pixels */
+
+ unsigned writable:1; /**< writable shader resource */
+
+ union {
+ struct {
+ unsigned level;
+ unsigned first_layer:16;
+ unsigned last_layer:16;
+ } tex;
+ struct {
+ unsigned first_element;
+ unsigned last_element;
+ } buf;
+ } u;
+};
+
+
+/**
+ * A view into a texture that can be bound to a shader stage.
+ */
+struct pipe_sampler_view
+{
+ /* struct pipe_reference reference; */
+ enum pipe_format format; /**< typed PIPE_FORMAT_x */
+ struct pipe_resource *texture; /**< texture into which this is a view */
+ struct pipe_context *context; /**< context this view belongs to */
+ union {
+ struct {
+ unsigned first_layer:16; /**< first layer to use for array textures */
+ unsigned last_layer:16; /**< last layer to use for array textures */
+ unsigned first_level:8; /**< first mipmap level to use */
+ unsigned last_level:8; /**< last mipmap level to use */
+ } tex;
+ struct {
+ unsigned first_element;
+ unsigned last_element;
+ } buf;
+ } u;
+ unsigned swizzle_r:3; /**< PIPE_SWIZZLE_x for red component */
+ unsigned swizzle_g:3; /**< PIPE_SWIZZLE_x for green component */
+ unsigned swizzle_b:3; /**< PIPE_SWIZZLE_x for blue component */
+ unsigned swizzle_a:3; /**< PIPE_SWIZZLE_x for alpha component */
+};
+
+#endif
+
diff --git a/native/fb/mip_cube.c b/native/fb/mip_cube.c
index 680c4b8..1e9bc38 100644
--- a/native/fb/mip_cube.c
+++ b/native/fb/mip_cube.c
@@ -49,6 +49,7 @@
#include "etna_fb.h"
#include "etna_mem.h"
#include "etna_bswap.h"
+#include "etna_tex.h"
#include "esTransform.h"
#include "dds.h"
@@ -191,38 +192,6 @@ uint32_t ps[] = { /* texture sampling */
size_t vs_size = sizeof(vs);
size_t ps_size = sizeof(ps);
-void etna_texture_tile(void *dest, void *src, unsigned width, unsigned height, unsigned src_stride, unsigned elmtsize)
-{
-#define TEX_TILE_WIDTH (4)
-#define TEX_TILE_HEIGHT (4)
-#define TEX_TILE_WORDS (TEX_TILE_WIDTH*TEX_TILE_HEIGHT)
- unsigned ytiles = height / TEX_TILE_HEIGHT;
- unsigned xtiles = width / TEX_TILE_WIDTH;
- unsigned dst_stride = xtiles * TEX_TILE_WORDS;
- if(elmtsize == 4)
- {
- src_stride >>= 2;
-
- for(unsigned ty=0; ty<ytiles; ++ty)
- {
- for(unsigned tx=0; tx<xtiles; ++tx)
- {
- unsigned ofs = ty * dst_stride + tx * TEX_TILE_WORDS;
- for(unsigned y=0; y<TEX_TILE_HEIGHT; ++y)
- {
- for(unsigned x=0; x<TEX_TILE_WIDTH; ++x)
- {
- unsigned srcy = ty*TEX_TILE_HEIGHT + y;
- unsigned srcx = tx*TEX_TILE_WIDTH + x;
- ((uint32_t*)dest)[ofs] = ((uint32_t*)src)[srcy*src_stride+srcx];
- ofs += 1;
- }
- }
- }
- }
- }
-}
-
int main(int argc, char **argv)
{
int rv;
diff --git a/native/fb/mip_cube_state.c b/native/fb/mip_cube_state.c
index 3ed459c..3090173 100644
--- a/native/fb/mip_cube_state.c
+++ b/native/fb/mip_cube_state.c
@@ -50,9 +50,11 @@
#include "etna_fb.h"
#include "etna_mem.h"
#include "etna_bswap.h"
+#include "etna_tex.h"
#include "esTransform.h"
#include "dds.h"
+#include "minigallium.h"
#define RCPLOG2 (1.4426950408889634f)
#define VERTEX_BUFFER_SIZE 0x60000
@@ -192,37 +194,6 @@ uint32_t ps[] = { /* texture sampling */
size_t vs_size = sizeof(vs);
size_t ps_size = sizeof(ps);
-void etna_texture_tile(void *dest, void *src, unsigned width, unsigned height, unsigned src_stride, unsigned elmtsize)
-{
-#define TEX_TILE_WIDTH (4)
-#define TEX_TILE_HEIGHT (4)
-#define TEX_TILE_WORDS (TEX_TILE_WIDTH*TEX_TILE_HEIGHT)
- unsigned ytiles = height / TEX_TILE_HEIGHT;
- unsigned xtiles = width / TEX_TILE_WIDTH;
- unsigned dst_stride = xtiles * TEX_TILE_WORDS;
- if(elmtsize == 4)
- {
- src_stride >>= 2;
-
- for(unsigned ty=0; ty<ytiles; ++ty)
- {
- for(unsigned tx=0; tx<xtiles; ++tx)
- {
- unsigned ofs = ty * dst_stride + tx * TEX_TILE_WORDS;
- for(unsigned y=0; y<TEX_TILE_HEIGHT; ++y)
- {
- for(unsigned x=0; x<TEX_TILE_WIDTH; ++x)
- {
- unsigned srcy = ty*TEX_TILE_HEIGHT + y;
- unsigned srcx = tx*TEX_TILE_WIDTH + x;
- ((uint32_t*)dest)[ofs] = ((uint32_t*)src)[srcy*src_stride+srcx];
- ofs += 1;
- }
- }
- }
- }
- }
-}
enum etna_surface_tiling
{
@@ -405,6 +376,542 @@ void compile_rs_state(struct state_packet *pkt, const struct rs_state *rs)
state[ptr++] = VIVS_RS_EXTRA_CONFIG_AA(rs->aa) | VIVS_RS_EXTRA_CONFIG_ENDIAN(rs->endian_mode);
}
+/*********************************************************************/
+/** Gallium state translation, WIP */
+
+/* Define state */
+#define SET_STATE(addr, value) state[addr/4] = (value)
+#define SET_STATE_FIXP(addr, value) state[addr/4] = (value)
+#define SET_STATE_F32(addr, value) state[addr/4] = f32_to_u32(value)
+/* [0.0 .. 1.0] -> [0 .. 255] */
+static inline uint8_t cfloat_to_uint8(float f)
+{
+ if(f<=0.0f) return 0;
+ if(f>=1.0f) return 255;
+ return f * 256.0f;
+}
+
+/* float to fixp 5.5 */
+static inline uint32_t float_to_fixp55(float f)
+{
+ return (uint32_t) (f * 32.0f + 0.5f);
+}
+
+/* texture size to log2 in fixp 5.5 format */
+static inline uint32_t log2_fixp55(unsigned width)
+{
+ return float_to_fixp55(logf((float)width) * RCPLOG2);
+}
+
+static inline uint32_t f32_to_u32(float value)
+{
+ union {
+ uint32_t u32;
+ float f32;
+ } x = { .f32 = value };
+ return x.u32;
+}
+
+static inline uint32_t translate_cull_face(unsigned cull_face, unsigned front_ccw)
+{
+ switch(cull_face) /* XXX verify this is the right way around */
+ {
+ case PIPE_FACE_NONE: return VIVS_PA_CONFIG_CULL_FACE_MODE_OFF;
+ case PIPE_FACE_FRONT: return front_ccw ? VIVS_PA_CONFIG_CULL_FACE_MODE_CCW : VIVS_PA_CONFIG_CULL_FACE_MODE_CW;
+ case PIPE_FACE_BACK: return front_ccw ? VIVS_PA_CONFIG_CULL_FACE_MODE_CW : VIVS_PA_CONFIG_CULL_FACE_MODE_CCW;
+ default: printf("Unhandled cull face mode %i\n", cull_face); return 0;
+ }
+}
+
+static inline uint32_t translate_polygon_mode(unsigned polygon_mode)
+{
+ switch(polygon_mode)
+ {
+ case PIPE_POLYGON_MODE_FILL: return VIVS_PA_CONFIG_FILL_MODE_SOLID;
+ case PIPE_POLYGON_MODE_LINE: return VIVS_PA_CONFIG_FILL_MODE_WIREFRAME;
+ case PIPE_POLYGON_MODE_POINT: return VIVS_PA_CONFIG_FILL_MODE_POINT;
+ default: printf("Unhandled polygon mode %i\n", polygon_mode); return 0;
+ }
+}
+
+static inline uint32_t translate_stencil_mode(bool enable_0, bool enable_1)
+{
+ if(enable_0)
+ {
+ return enable_1 ? VIVS_PE_STENCIL_CONFIG_MODE_TWO_SIDED :
+ VIVS_PE_STENCIL_CONFIG_MODE_ONE_SIDED;
+ } else {
+ return VIVS_PE_STENCIL_CONFIG_MODE_DISABLED;
+ }
+}
+
+static inline uint32_t translate_stencil_op(unsigned stencil_op)
+{
+ switch(stencil_op)
+ {
+ case PIPE_STENCIL_OP_KEEP: return STENCIL_OP_KEEP;
+ case PIPE_STENCIL_OP_ZERO: return STENCIL_OP_ZERO;
+ case PIPE_STENCIL_OP_REPLACE: return STENCIL_OP_REPLACE;
+ case PIPE_STENCIL_OP_INCR: return STENCIL_OP_INCR;
+ case PIPE_STENCIL_OP_DECR: return STENCIL_OP_DECR;
+ case PIPE_STENCIL_OP_INCR_WRAP: return STENCIL_OP_INCR_WRAP;
+ case PIPE_STENCIL_OP_DECR_WRAP: return STENCIL_OP_DECR_WRAP;
+ case PIPE_STENCIL_OP_INVERT: return STENCIL_OP_INVERT;
+ default: printf("Unhandled stencil op: %i\n", stencil_op); return 0;
+ }
+}
+
+static inline uint32_t translate_blend(unsigned blend)
+{
+ switch(blend)
+ {
+ case PIPE_BLEND_ADD: return BLEND_EQ_ADD;
+ case PIPE_BLEND_SUBTRACT: return BLEND_EQ_SUBTRACT;
+ case PIPE_BLEND_REVERSE_SUBTRACT: return BLEND_EQ_REVERSE_SUBTRACT;
+ case PIPE_BLEND_MIN: return BLEND_EQ_MIN;
+ case PIPE_BLEND_MAX: return BLEND_EQ_MAX;
+ default: printf("Unhandled blend: %i\n", blend); return 0;
+ }
+}
+
+static inline uint32_t translate_blend_factor(unsigned blend_factor)
+{
+ switch(blend_factor)
+ {
+ case PIPE_BLENDFACTOR_ONE: return BLEND_FUNC_ONE;
+ case PIPE_BLENDFACTOR_SRC_COLOR: return BLEND_FUNC_SRC_COLOR;
+ case PIPE_BLENDFACTOR_SRC_ALPHA: return BLEND_FUNC_SRC_ALPHA;
+ case PIPE_BLENDFACTOR_DST_ALPHA: return BLEND_FUNC_DST_ALPHA;
+ case PIPE_BLENDFACTOR_DST_COLOR: return BLEND_FUNC_DST_COLOR;
+ case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: return BLEND_FUNC_SRC_ALPHA_SATURATE;
+ case PIPE_BLENDFACTOR_CONST_COLOR: return BLEND_FUNC_CONSTANT_COLOR;
+ case PIPE_BLENDFACTOR_CONST_ALPHA: return BLEND_FUNC_CONSTANT_ALPHA;
+ case PIPE_BLENDFACTOR_ZERO: return BLEND_FUNC_ZERO;
+ case PIPE_BLENDFACTOR_INV_SRC_COLOR: return BLEND_FUNC_ONE_MINUS_SRC_COLOR;
+ case PIPE_BLENDFACTOR_INV_SRC_ALPHA: return BLEND_FUNC_ONE_MINUS_SRC_ALPHA;
+ case PIPE_BLENDFACTOR_INV_DST_ALPHA: return BLEND_FUNC_ONE_MINUS_DST_ALPHA;
+ case PIPE_BLENDFACTOR_INV_DST_COLOR: return BLEND_FUNC_ONE_MINUS_DST_COLOR;
+ case PIPE_BLENDFACTOR_INV_CONST_COLOR: return BLEND_FUNC_ONE_MINUS_CONSTANT_COLOR;
+ case PIPE_BLENDFACTOR_INV_CONST_ALPHA: return BLEND_FUNC_ONE_MINUS_CONSTANT_ALPHA;
+ case PIPE_BLENDFACTOR_SRC1_COLOR:
+ case PIPE_BLENDFACTOR_SRC1_ALPHA:
+ case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+ case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
+ default: printf("Unhandled blend factor: %i\n", blend_factor); return 0;
+ }
+}
+
+static inline uint32_t translate_texture_wrapmode(unsigned wrap)
+{
+ switch(wrap)
+ {
+ case PIPE_TEX_WRAP_REPEAT: return TEXTURE_WRAPMODE_REPEAT;
+ case PIPE_TEX_WRAP_CLAMP: return TEXTURE_WRAPMODE_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return TEXTURE_WRAPMODE_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return TEXTURE_WRAPMODE_CLAMP_TO_EDGE; /* XXX */
+ case PIPE_TEX_WRAP_MIRROR_REPEAT: return TEXTURE_WRAPMODE_MIRRORED_REPEAT;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP: return TEXTURE_WRAPMODE_MIRRORED_REPEAT; /* XXX */
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return TEXTURE_WRAPMODE_MIRRORED_REPEAT; /* XXX */
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return TEXTURE_WRAPMODE_MIRRORED_REPEAT; /* XXX */
+ default: printf("Unhandled texture wrapmode: %i\n", wrap); return 0;
+ }
+}
+
+static inline uint32_t translate_texture_mipfilter(unsigned filter)
+{
+ switch(filter)
+ {
+ case PIPE_TEX_MIPFILTER_NEAREST: return TEXTURE_FILTER_NEAREST;
+ case PIPE_TEX_MIPFILTER_LINEAR: return TEXTURE_FILTER_LINEAR;
+ case PIPE_TEX_MIPFILTER_NONE: return TEXTURE_FILTER_NONE;
+ default: printf("Unhandled texture mipfilter: %i\n", filter); return 0;
+ }
+}
+
+static inline uint32_t translate_texture_filter(unsigned filter)
+{
+ switch(filter)
+ {
+ case PIPE_TEX_FILTER_NEAREST: return TEXTURE_FILTER_NEAREST;
+ case PIPE_TEX_FILTER_LINEAR: return TEXTURE_FILTER_LINEAR;
+ default: printf("Unhandled texture filter: %i\n", filter); return 0;
+ }
+}
+
+static inline uint32_t translate_texture_format(enum pipe_format fmt)
+{
+ /* XXX these are all reversed - does it matter? */
+ switch(fmt) /* XXX with TEXTURE_FORMAT_EXT and swizzle on newer chips we can support much more */
+ {
+ case PIPE_FORMAT_A8_UNORM: return TEXTURE_FORMAT_A8;
+ case PIPE_FORMAT_L8_UNORM: return TEXTURE_FORMAT_L8;
+ case PIPE_FORMAT_I8_UNORM: return TEXTURE_FORMAT_I8;
+ case PIPE_FORMAT_L8A8_UNORM: return TEXTURE_FORMAT_A8L8;
+ case PIPE_FORMAT_B4G4R4A4_UNORM: return TEXTURE_FORMAT_A4R4G4B4;
+ case PIPE_FORMAT_B4G4R4X4_UNORM: return TEXTURE_FORMAT_X4R4G4B4;
+ case PIPE_FORMAT_A8R8G8B8_UNORM: return TEXTURE_FORMAT_A8R8G8B8;
+ case PIPE_FORMAT_X8R8G8B8_UNORM: return TEXTURE_FORMAT_X8R8G8B8;
+ case PIPE_FORMAT_A8B8G8R8_UNORM: return TEXTURE_FORMAT_A8B8G8R8;
+ case PIPE_FORMAT_R8G8B8X8_UNORM: return TEXTURE_FORMAT_X8B8G8R8;
+ case PIPE_FORMAT_B5G6R5_UNORM: return TEXTURE_FORMAT_R5G6B5;
+ case PIPE_FORMAT_B5G5R5A1_UNORM: return TEXTURE_FORMAT_A1R5G5B5;
+ case PIPE_FORMAT_B5G5R5X1_UNORM: return TEXTURE_FORMAT_X1R5G5B5;
+ case PIPE_FORMAT_YUYV: return TEXTURE_FORMAT_YUY2;
+ case PIPE_FORMAT_UYVY: return TEXTURE_FORMAT_UYVY;
+ case PIPE_FORMAT_Z16_UNORM: return TEXTURE_FORMAT_D16;
+ case PIPE_FORMAT_Z24X8_UNORM: return TEXTURE_FORMAT_D24S8;
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT: return TEXTURE_FORMAT_D24S8;
+ case PIPE_FORMAT_DXT1_RGB: return TEXTURE_FORMAT_DXT1;
+ case PIPE_FORMAT_DXT1_RGBA: return TEXTURE_FORMAT_DXT1;
+ case PIPE_FORMAT_DXT3_RGBA: return TEXTURE_FORMAT_DXT2_DXT3;
+ case PIPE_FORMAT_DXT5_RGBA: return TEXTURE_FORMAT_DXT4_DXT5;
+ case PIPE_FORMAT_ETC1_RGB8: return TEXTURE_FORMAT_ETC1;
+ default: printf("Unhandled texture format: %i\n", fmt); return 0;
+ }
+}
+
+/* render target format */
+static inline uint32_t translate_rt_format(enum pipe_format fmt)
+{
+ /* XXX these are all reversed - does it matter? */
+ switch(fmt)
+ {
+ case PIPE_FORMAT_B4G4R4X4_UNORM: return RS_FORMAT_X4R4G4B4;
+ case PIPE_FORMAT_B4G4R4A4_UNORM: return RS_FORMAT_A4R4G4B4;
+ case PIPE_FORMAT_B5G5R5X1_UNORM: return RS_FORMAT_X1R5G5B5;
+ case PIPE_FORMAT_B5G5R5A1_UNORM: return RS_FORMAT_A1R5G5B5;
+ case PIPE_FORMAT_B5G6R5_UNORM: return RS_FORMAT_R5G6B5;
+ case PIPE_FORMAT_X8R8G8B8_UNORM: return RS_FORMAT_X8R8G8B8;
+ case PIPE_FORMAT_A8R8G8B8_UNORM: return RS_FORMAT_A8R8G8B8;
+ case PIPE_FORMAT_YUYV: return RS_FORMAT_YUY2;
+ default: printf("Unhandled rs surface format: %i\n", fmt); return 0;
+ }
+}
+
+static inline uint32_t translate_depth_format(enum pipe_format fmt)
+{
+ switch(fmt)
+ {
+ case PIPE_FORMAT_Z16_UNORM: return VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16;
+ case PIPE_FORMAT_Z24X8_UNORM: return VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D24S8;
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT: return VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D24S8;
+ default: printf("Unhandled depth format: %i\n", fmt); return 0;
+ }
+}
+
+/* render target format for MSAA */
+static inline uint32_t translate_msaa_format(enum pipe_format fmt)
+{
+ switch(fmt)
+ {
+ case PIPE_FORMAT_B4G4R4X4_UNORM: return VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A4R4G4B4;
+ case PIPE_FORMAT_B4G4R4A4_UNORM: return VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A4R4G4B4;
+ case PIPE_FORMAT_B5G5R5X1_UNORM: return VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A1R5G5B5;
+ case PIPE_FORMAT_B5G5R5A1_UNORM: return VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A1R5G5B5;
+ case PIPE_FORMAT_B5G6R5_UNORM: return VIVS_TS_MEM_CONFIG_MSAA_FORMAT_R5G6B5;
+ case PIPE_FORMAT_X8R8G8B8_UNORM: return VIVS_TS_MEM_CONFIG_MSAA_FORMAT_X8R8G8B8;
+ case PIPE_FORMAT_A8R8G8B8_UNORM: return VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8;
+ /* MSAA with YUYV not supported */
+ default: printf("Unhandled msaa surface format: %i\n", fmt); return 0;
+ }
+}
+
+static inline uint32_t translate_texture_target(enum pipe_texture_target tgt)
+{
+ switch(tgt)
+ {
+ case PIPE_TEXTURE_2D: return TEXTURE_TYPE_2D;
+ case PIPE_TEXTURE_CUBE: return TEXTURE_TYPE_CUBE_MAP;
+ default: printf("Unhandled texture target: %i\n", tgt); return 0;
+ }
+}
+
+/*********************************************************************/
+/** Gallium state compilation, WIP */
+
+/* extra state not represented in pipe_framebuffer_state */
+struct etna_framebuffer_state
+{
+ unsigned padded_width;
+ unsigned padded_height;
+ uint32_t color_rt;
+ uint32_t color_ts;
+ uint32_t depth_rt;
+ uint32_t depth_ts;
+};
+/* extra state not represented in pipe_resource */
+struct etna_resource
+{
+ uint32_t lod_addr[VIVS_TE_SAMPLER_LOD_ADDR__LEN];
+};
+
+void compile_rasterizer_state(struct state_packet *pkt, const struct pipe_rasterizer_state *rs)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ if(rs->fill_front != rs->fill_back)
+ {
+ printf("Different front and back fill mode not supported\n");
+ }
+ SET_STATE(VIVS_PA_CONFIG,
+ (rs->flatshade ? VIVS_PA_CONFIG_SHADE_MODEL_FLAT : VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH) |
+ translate_cull_face(rs->cull_face, rs->front_ccw) |
+ translate_polygon_mode(rs->fill_front) |
+ (rs->point_quad_rasterization ? VIVS_PA_CONFIG_POINT_SPRITE_ENABLE : 0) |
+ (rs->point_size_per_vertex ? VIVS_PA_CONFIG_POINT_SIZE_ENABLE : 0));
+ SET_STATE(VIVS_SE_CONFIG,
+ (rs->line_last_pixel ? VIVS_SE_CONFIG_LAST_PIXEL_ENABLE : 0)
+ /* XXX anything else? */
+ );
+ SET_STATE_F32(VIVS_PA_LINE_WIDTH, rs->line_width);
+ SET_STATE_F32(VIVS_PA_POINT_SIZE, rs->point_size);
+ SET_STATE_F32(VIVS_SE_DEPTH_SCALE, rs->offset_scale);
+ SET_STATE_F32(VIVS_SE_DEPTH_BIAS, rs->offset_units);
+ /* XXX rs->gl_rasterization_rules is likely one of the bits in VIVS_PA_SYSTEM_MODE */
+ /* XXX rs->scissor as well as pipe_scissor_state affects VIVS_SE_SCISSOR_* */
+}
+
+
+void compile_depth_stencil_alpha_state(struct state_packet *pkt, const struct pipe_depth_stencil_alpha_state *dsa)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ /* XXX does stencil[0] / stencil[1] depend on rs->front_ccw? */
+ /* compare funcs have 1 to 1 mapping */
+ SET_STATE(VIVS_PE_DEPTH_CONFIG,
+ VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(dsa->depth.enabled ? dsa->depth.func : PIPE_FUNC_ALWAYS) |
+ (dsa->depth.writemask ? VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE : 0)
+ /* XXX DEPTH_FORMAT, DEPTH_MODE, SUPER_TILED, EARLY_Z */
+ );
+ SET_STATE(VIVS_PE_ALPHA_OP,
+ (dsa->alpha.enabled ? VIVS_PE_ALPHA_OP_ALPHA_TEST : 0) |
+ VIVS_PE_ALPHA_OP_ALPHA_FUNC(dsa->alpha.func) |
+ VIVS_PE_ALPHA_OP_ALPHA_REF(cfloat_to_uint8(dsa->alpha.ref_value)));
+ SET_STATE(VIVS_PE_STENCIL_OP,
+ VIVS_PE_STENCIL_OP_FUNC_FRONT(dsa->stencil[0].func) |
+ VIVS_PE_STENCIL_OP_FUNC_BACK(dsa->stencil[1].func) |
+ VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(dsa->stencil[0].fail_op)) |
+ VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(dsa->stencil[1].fail_op)) |
+ VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(dsa->stencil[0].zfail_op)) |
+ VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(dsa->stencil[1].zfail_op)) |
+ VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(dsa->stencil[0].zpass_op)) |
+ VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(dsa->stencil[1].zpass_op)));
+ SET_STATE(VIVS_PE_STENCIL_CONFIG,
+ translate_stencil_mode(dsa->stencil[0].enabled, dsa->stencil[1].enabled) |
+ VIVS_PE_STENCIL_CONFIG_MASK_FRONT(dsa->stencil[0].valuemask) |
+ VIVS_PE_STENCIL_CONFIG_WRITE_MASK(dsa->stencil[0].writemask)
+ /* XXX back masks in VIVS_PE_DEPTH_CONFIG_EXT? */
+ /* XXX VIVS_PE_STENCIL_CONFIG_REF_FRONT comes from pipe_stencil_ref */
+ );
+ /* XXX PE_COLOR_FORMAT_PARTIAL? */
+}
+
+
+void compile_blend_state(struct state_packet *pkt, const struct pipe_blend_state *bs)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ const struct pipe_rt_blend_state *rt0 = &bs->rt[0];
+ bool enable = rt0->blend_enable && !(rt0->rgb_src_factor == PIPE_BLENDFACTOR_ONE && rt0->rgb_dst_factor == PIPE_BLENDFACTOR_ZERO &&
+ rt0->alpha_src_factor == PIPE_BLENDFACTOR_ONE && rt0->alpha_dst_factor == PIPE_BLENDFACTOR_ZERO);
+ bool separate_alpha = enable && !(rt0->rgb_src_factor == rt0->alpha_src_factor &&
+ rt0->rgb_dst_factor == rt0->alpha_dst_factor);
+ SET_STATE(VIVS_PE_ALPHA_CONFIG,
+ (enable ? VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR : 0) |
+ (separate_alpha ? VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA : 0) |
+ VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(translate_blend_factor(rt0->rgb_src_factor)) |
+ VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(translate_blend_factor(rt0->alpha_src_factor)) |
+ VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(translate_blend_factor(rt0->rgb_dst_factor)) |
+ VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(translate_blend_factor(rt0->alpha_dst_factor)) |
+ VIVS_PE_ALPHA_CONFIG_EQ_COLOR(translate_blend(rt0->rgb_func)) |
+ VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(translate_blend(rt0->alpha_func))
+ );
+ SET_STATE(VIVS_PE_COLOR_FORMAT,
+ VIVS_PE_COLOR_FORMAT_COMPONENTS(rt0->colormask)
+ /* XXX COLOR_FORMAT, PARTIAL, SUPER_TILED */
+ );
+ SET_STATE(VIVS_PE_LOGIC_OP,
+ VIVS_PE_LOGIC_OP_OP(bs->logicop_enable ? bs->logicop_func : LOGIC_OP_COPY) /* 1-to-1 mapping */ |
+ 0x000E4000 /* ??? */
+ );
+ /* independent_blend_enable not needed: only one rt supported */
+ /* XXX alpha_to_coverage / alpha_to_one? */
+ /* XXX dither? VIVS_PE_DITHER(...) and/or VIVS_RS_DITHER(...) on resolve */
+}
+
+void compile_blend_color(struct state_packet *pkt, const struct pipe_blend_color *bc)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ SET_STATE(VIVS_PE_ALPHA_BLEND_COLOR,
+ VIVS_PE_ALPHA_BLEND_COLOR_R(cfloat_to_uint8(bc->color[0])) |
+ VIVS_PE_ALPHA_BLEND_COLOR_G(cfloat_to_uint8(bc->color[1])) |
+ VIVS_PE_ALPHA_BLEND_COLOR_B(cfloat_to_uint8(bc->color[2])) |
+ VIVS_PE_ALPHA_BLEND_COLOR_A(cfloat_to_uint8(bc->color[3]))
+ );
+}
+
+void compile_stencil_ref(struct state_packet *pkt, const struct pipe_stencil_ref *sr)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ SET_STATE(VIVS_PE_STENCIL_CONFIG,
+ VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0])
+ /* XXX rest comes from depth_stencil_alpha, need to merge in */
+ );
+ SET_STATE(VIVS_PE_STENCIL_CONFIG_EXT,
+ VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0])
+ );
+}
+
+void compile_scissor_state(struct state_packet *pkt, const struct pipe_scissor_state *ss)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ SET_STATE_FIXP(VIVS_SE_SCISSOR_LEFT, (ss->minx << 16));
+ SET_STATE_FIXP(VIVS_SE_SCISSOR_TOP, (ss->miny << 16));
+ SET_STATE_FIXP(VIVS_SE_SCISSOR_RIGHT, (ss->maxx << 16)-1);
+ SET_STATE_FIXP(VIVS_SE_SCISSOR_BOTTOM, (ss->maxy << 16)-1);
+ /* XXX note that rasterizer state scissor also affects this, if it's disabled scissor spans the full framebuffer
+ * also, this is affected by framebuffer: scissor is always bounded by framebuffer */
+}
+
+void compile_viewport_state(struct state_packet *pkt, const struct pipe_viewport_state *vs)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ /**
+ * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of -1..1 to 0..1.
+ * scaling and translation to 0..1 already happened, so remove that
+ *
+ * z' = (z * 2 - 1) * scale + translate
+ * = z * (2 * scale) + (translate - scale)
+ *
+ * scale' = 2 * scale
+ * translate' = translate - scale
+ */
+ SET_STATE_F32(VIVS_PA_VIEWPORT_SCALE_X, vs->scale[0]); /* XXX must this be fixp? */
+ SET_STATE_F32(VIVS_PA_VIEWPORT_SCALE_Y, vs->scale[1]); /* XXX must this be fixp? */
+ SET_STATE_F32(VIVS_PA_VIEWPORT_SCALE_Z, vs->scale[2] * 2.0f);
+ SET_STATE_F32(VIVS_PA_VIEWPORT_OFFSET_X, vs->translate[0]); /* XXX must this be fixp? */
+ SET_STATE_F32(VIVS_PA_VIEWPORT_OFFSET_Y, vs->translate[1]); /* XXX must this be fixp? */
+ SET_STATE_F32(VIVS_PA_VIEWPORT_OFFSET_Z, vs->translate[2] - vs->scale[2]);
+
+ SET_STATE_F32(VIVS_PE_DEPTH_NEAR, 0.0); /* not affected if depth mode is Z (as in GL) */
+ SET_STATE_F32(VIVS_PE_DEPTH_FAR, 1.0);
+}
+
+void compile_sample_mask(struct state_packet *pkt, unsigned sample_mask)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ SET_STATE(VIVS_GL_MULTI_SAMPLE_CONFIG,
+ /* XXX to be merged with render target state */
+ VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(sample_mask));
+}
+
+/* sampler offset +4*sampler */
+void compile_sampler_state(struct state_packet *pkt, const struct pipe_sampler_state *ss)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ SET_STATE(VIVS_TE_SAMPLER_CONFIG0(0),
+ /* XXX get from sampler view: VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D)| */
+ VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s))|
+ VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t))|
+ VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter))|
+ VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter))|
+ VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter))
+ /* XXX get from sampler view: VIVS_TE_SAMPLER_CONFIG0_FORMAT(tex_format) */
+ );
+ /* VIVS_TE_SAMPLER_CONFIG1 (swizzle, extended format) fully determined by sampler view */
+ SET_STATE(VIVS_TE_SAMPLER_LOD_CONFIG(0),
+ (ss->lod_bias != 0.0 ? VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE : 0) |
+ VIVS_TE_SAMPLER_LOD_CONFIG_MAX(float_to_fixp55(ss->max_lod)) | /* XXX min((sampler_view->last_level<<5) - 1, ...) or you're in for some crashes */
+ VIVS_TE_SAMPLER_LOD_CONFIG_MIN(float_to_fixp55(ss->min_lod)) | /* XXX max((sampler_view->first_level<<5), ...) */
+ VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(float_to_fixp55(ss->lod_bias))
+ );
+}
+
+void compile_sampler_view(struct state_packet *pkt, const struct pipe_sampler_view *sv,
+ struct etna_resource *esv)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ struct pipe_resource *res = sv->texture;
+ assert(res != NULL && esv != NULL);
+
+ SET_STATE(VIVS_TE_SAMPLER_CONFIG0(0),
+ VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(res->target)) |
+ VIVS_TE_SAMPLER_CONFIG0_FORMAT(translate_texture_format(sv->format))
+ /* XXX merged with sampler state */
+ );
+ /* XXX VIVS_TE_SAMPLER_CONFIG1 (swizzle, extended format), swizzle_(r|g|b|a) */
+ SET_STATE(VIVS_TE_SAMPLER_SIZE(0),
+ VIVS_TE_SAMPLER_SIZE_WIDTH(res->width0)|
+ VIVS_TE_SAMPLER_SIZE_HEIGHT(res->height0));
+ SET_STATE(VIVS_TE_SAMPLER_LOG_SIZE(0),
+ VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(log2_fixp55(res->width0)) |
+ VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(log2_fixp55(res->height0)));
+ /* XXX in principle we only have to define lods sv->first_level .. sv->last_level */
+ for(int lod=0; lod<=res->last_level; ++lod)
+ {
+ SET_STATE(VIVS_TE_SAMPLER_LOD_ADDR(0, lod), esv->lod_addr[lod]);
+ }
+}
+
+void compile_framebuffer_state(struct state_packet *pkt, const struct pipe_framebuffer_state *sv,
+ const struct etna_framebuffer_state *esv)
+{
+ uint32_t state[65536];
+ int ptr = 0;
+ /* XXX support Z24S8 depth format */
+ struct pipe_surface *cbuf = (sv->nr_cbufs > 0) ? sv->cbufs[0] : NULL;
+ struct pipe_surface *zsbuf = sv->zsbuf;
+ /* XXX rendering with only color or only depth */
+ assert(cbuf != NULL && zsbuf != NULL && esv != NULL);
+ unsigned depth_bits = 16;
+
+ SET_STATE(VIVS_PE_COLOR_FORMAT,
+ VIVS_PE_COLOR_FORMAT_FORMAT(translate_rt_format(cbuf->format)) |
+ VIVS_PE_COLOR_FORMAT_SUPER_TILED /* XXX depends on layout */
+ /* XXX VIVS_PE_COLOR_FORMAT_PARTIAL and the rest comes from depth_stencil_alpha */
+ ); /* merged with depth_stencil_alpha */
+ SET_STATE(VIVS_PE_DEPTH_CONFIG,
+ translate_depth_format(zsbuf->format) |
+ VIVS_PE_DEPTH_CONFIG_SUPER_TILED | /* XXX depends on layout */
+ VIVS_PE_DEPTH_CONFIG_EARLY_Z |
+ VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z
+ /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
+ ); /* merged with depth_stencil_alpha */
+ SET_STATE(VIVS_PE_DEPTH_ADDR, esv->depth_rt);
+ SET_STATE(VIVS_PE_DEPTH_STRIDE, esv->padded_width * 2); // XXX should depend on depth format
+ SET_STATE(VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED);
+ SET_STATE_F32(VIVS_PE_DEPTH_NORMALIZE, exp2f(depth_bits) - 1.0f);
+ SET_STATE(VIVS_PE_COLOR_ADDR, esv->color_rt);
+ SET_STATE(VIVS_PE_COLOR_STRIDE, esv->padded_width * 4); // XXX should depend on color format
+
+ SET_STATE_FIXP(VIVS_SE_SCISSOR_LEFT, 0); /* affected by rasterizer and scissor state as well */
+ SET_STATE_FIXP(VIVS_SE_SCISSOR_TOP, 0);
+ SET_STATE_FIXP(VIVS_SE_SCISSOR_RIGHT, (sv->width << 16)-1);
+ SET_STATE_FIXP(VIVS_SE_SCISSOR_BOTTOM, (sv->height << 16)-1);
+
+ /* Set up TS as well */
+ SET_STATE(VIVS_TS_MEM_CONFIG,
+ VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
+ VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
+ (depth_bits == 16 ? VIVS_TS_MEM_CONFIG_DEPTH_16BPP : 0) |
+ VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
+ SET_STATE(VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff); // XXX remember depth/stencil clear value from ->clear
+ SET_STATE(VIVS_TS_DEPTH_STATUS_BASE, esv->depth_ts);
+ SET_STATE(VIVS_TS_DEPTH_SURFACE_BASE, esv->depth_rt);
+ SET_STATE(VIVS_TS_COLOR_CLEAR_VALUE, 0xff303030); // XXX remember clear color from ->clear
+ SET_STATE(VIVS_TS_COLOR_STATUS_BASE, esv->color_ts);
+ SET_STATE(VIVS_TS_COLOR_SURFACE_BASE, esv->color_rt);
+}
+
+/*********************************************************************/
+
/* compare old and new state packet, submit difference to queue */
void diff_state_packet(etna_ctx *restrict ctx, const struct state_packet_desc *restrict pdesc, const uint32_t *restrict oldvalues, const uint32_t *restrict newvalues)
{
@@ -824,7 +1331,6 @@ int main(int argc, char **argv)
VIVS_TE_SAMPLER_LOD_CONFIG_MAX((dds->num_mipmaps - 1)<<5) | VIVS_TE_SAMPLER_LOD_CONFIG_MIN(0));
/* shader setup */
-
etna_set_state(ctx, VIVS_VS_START_PC, 0x0);
etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16);
etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){
diff --git a/native/fb/rotate_cube.c b/native/fb/rotate_cube.c
index acccae0..82576fd 100644
--- a/native/fb/rotate_cube.c
+++ b/native/fb/rotate_cube.c
@@ -293,7 +293,7 @@ int main(int argc, char **argv)
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0));
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
- ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) &
+ ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
diff --git a/native/include/etna/cmdstream.xml.h b/native/include/etna/cmdstream.xml.h
index 36b7c54..1e58fa2 100644
--- a/native/include/etna/cmdstream.xml.h
+++ b/native/include/etna/cmdstream.xml.h
@@ -9,7 +9,7 @@ git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
- /home/orion/projects/etna_viv/rnndb/cmdstream.xml ( 11642 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/common.xml ( 15637 bytes, from 2013-02-01 10:14:07)
+- /home/orion/projects/etna_viv/rnndb/common.xml ( 15601 bytes, from 2013-02-01 12:03:20)
Copyright (C) 2013
*/
diff --git a/native/include/etna/common.xml.h b/native/include/etna/common.xml.h
index faa46d3..b41884e 100644
--- a/native/include/etna/common.xml.h
+++ b/native/include/etna/common.xml.h
@@ -8,11 +8,11 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/common.xml ( 15637 bytes, from 2013-02-01 10:14:07)
+- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-02 08:24:22)
+- /home/orion/projects/etna_viv/rnndb/common.xml ( 15601 bytes, from 2013-02-01 12:03:20)
- /home/orion/projects/etna_viv/rnndb/state_hi.xml ( 11825 bytes, from 2013-02-01 10:14:08)
- /home/orion/projects/etna_viv/rnndb/state_2d.xml ( 30577 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48941 bytes, from 2013-01-31 20:55:33)
+- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48960 bytes, from 2013-02-02 16:37:28)
Copyright (C) 2013
*/
diff --git a/native/include/etna/state.xml.h b/native/include/etna/state.xml.h
index 5ad8152..3e8e0a9 100644
--- a/native/include/etna/state.xml.h
+++ b/native/include/etna/state.xml.h
@@ -8,11 +8,11 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/common.xml ( 15637 bytes, from 2013-02-01 10:14:07)
+- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-02 08:24:22)
+- /home/orion/projects/etna_viv/rnndb/common.xml ( 15601 bytes, from 2013-02-01 12:03:20)
- /home/orion/projects/etna_viv/rnndb/state_hi.xml ( 11825 bytes, from 2013-02-01 10:14:08)
- /home/orion/projects/etna_viv/rnndb/state_2d.xml ( 30577 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48941 bytes, from 2013-01-31 20:55:33)
+- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48960 bytes, from 2013-02-02 16:37:28)
Copyright (C) 2013
*/
diff --git a/native/include/etna/state_2d.xml.h b/native/include/etna/state_2d.xml.h
index f245da2..ceabb27 100644
--- a/native/include/etna/state_2d.xml.h
+++ b/native/include/etna/state_2d.xml.h
@@ -8,11 +8,11 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/common.xml ( 15637 bytes, from 2013-02-01 10:14:07)
+- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-02 08:24:22)
+- /home/orion/projects/etna_viv/rnndb/common.xml ( 15601 bytes, from 2013-02-01 12:03:20)
- /home/orion/projects/etna_viv/rnndb/state_hi.xml ( 11825 bytes, from 2013-02-01 10:14:08)
- /home/orion/projects/etna_viv/rnndb/state_2d.xml ( 30577 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48941 bytes, from 2013-01-31 20:55:33)
+- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48960 bytes, from 2013-02-02 16:37:28)
Copyright (C) 2013
*/
diff --git a/native/include/etna/state_3d.xml.h b/native/include/etna/state_3d.xml.h
index 4a4b0b5..c3b31ab 100644
--- a/native/include/etna/state_3d.xml.h
+++ b/native/include/etna/state_3d.xml.h
@@ -8,11 +8,11 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/common.xml ( 15637 bytes, from 2013-02-01 10:14:07)
+- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-02 08:24:22)
+- /home/orion/projects/etna_viv/rnndb/common.xml ( 15601 bytes, from 2013-02-01 12:03:20)
- /home/orion/projects/etna_viv/rnndb/state_hi.xml ( 11825 bytes, from 2013-02-01 10:14:08)
- /home/orion/projects/etna_viv/rnndb/state_2d.xml ( 30577 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48941 bytes, from 2013-01-31 20:55:33)
+- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48960 bytes, from 2013-02-02 16:37:28)
Copyright (C) 2013
*/
@@ -111,6 +111,22 @@ Copyright (C) 2013
#define TEXTURE_SWIZZLE_ALPHA 0x00000003
#define TEXTURE_SWIZZLE_ZERO 0x00000004
#define TEXTURE_SWIZZLE_ONE 0x00000005
+#define LOGIC_OP_CLEAR 0x00000000
+#define LOGIC_OP_NOR 0x00000001
+#define LOGIC_OP_AND_INVERTED 0x00000002
+#define LOGIC_OP_COPY_INVERTED 0x00000003
+#define LOGIC_OP_AND_REVERSE 0x00000004
+#define LOGIC_OP_INVERT 0x00000005
+#define LOGIC_OP_XOR 0x00000006
+#define LOGIC_OP_NAND 0x00000007
+#define LOGIC_OP_AND 0x00000008
+#define LOGIC_OP_EQUIV 0x00000009
+#define LOGIC_OP_NOOP 0x0000000a
+#define LOGIC_OP_OR_INVERTED 0x0000000b
+#define LOGIC_OP_COPY 0x0000000c
+#define LOGIC_OP_OR_REVERSE 0x0000000d
+#define LOGIC_OP_OR 0x0000000e
+#define LOGIC_OP_SET 0x0000000f
#define VIVS_VS 0x00000000
#define VIVS_VS_END_PC 0x00000800
@@ -451,6 +467,10 @@ Copyright (C) 2013
#define VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT 4
#define VIVS_PE_ALPHA_OP_ALPHA_FUNC(x) (((x) << VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK)
#define VIVS_PE_ALPHA_OP_ALPHA_FUNC_MASK 0x00000080
+#define VIVS_PE_ALPHA_OP_ALPHA_REF__MASK 0x0000ff00
+#define VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT 8
+#define VIVS_PE_ALPHA_OP_ALPHA_REF(x) (((x) << VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_REF__MASK)
+#define VIVS_PE_ALPHA_OP_ALPHA_REF_MASKFUNC_MASK 0x00010000
#define VIVS_PE_ALPHA_BLEND_COLOR 0x00001424
#define VIVS_PE_ALPHA_BLEND_COLOR_B__MASK 0x000000ff
@@ -481,8 +501,8 @@ Copyright (C) 2013
#define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT 12
#define VIVS_PE_ALPHA_CONFIG_EQ_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK)
#define VIVS_PE_ALPHA_CONFIG_EQ_COLOR_MASK 0x00008000
-#define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA 0x00010000
-#define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA_MASK 0x00020000
+#define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA 0x00010000
+#define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA_MASK 0x00020000
#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA_MASK 0x00040000
#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK 0x00080000
#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK 0x00f00000
@@ -550,22 +570,7 @@ Copyright (C) 2013
#define VIVS_PE_LOGIC_OP 0x000014a4
#define VIVS_PE_LOGIC_OP_OP__MASK 0x0000000f
#define VIVS_PE_LOGIC_OP_OP__SHIFT 0
-#define VIVS_PE_LOGIC_OP_OP_CLEAR 0x00000000
-#define VIVS_PE_LOGIC_OP_OP_NOR 0x00000001
-#define VIVS_PE_LOGIC_OP_OP_AND_INVERTED 0x00000002
-#define VIVS_PE_LOGIC_OP_OP_COPY_INVERTED 0x00000003
-#define VIVS_PE_LOGIC_OP_OP_AND_REVERSE 0x00000004
-#define VIVS_PE_LOGIC_OP_OP_INVERT 0x00000005
-#define VIVS_PE_LOGIC_OP_OP_XOR 0x00000006
-#define VIVS_PE_LOGIC_OP_OP_NAND 0x00000007
-#define VIVS_PE_LOGIC_OP_OP_AND 0x00000008
-#define VIVS_PE_LOGIC_OP_OP_EQUIV 0x00000009
-#define VIVS_PE_LOGIC_OP_OP_NOOP 0x0000000a
-#define VIVS_PE_LOGIC_OP_OP_OR_INVERTED 0x0000000b
-#define VIVS_PE_LOGIC_OP_OP_COPY 0x0000000c
-#define VIVS_PE_LOGIC_OP_OP_OR_REVERSE 0x0000000d
-#define VIVS_PE_LOGIC_OP_OP_OR 0x0000000e
-#define VIVS_PE_LOGIC_OP_OP_SET 0x0000000f
+#define VIVS_PE_LOGIC_OP_OP(x) (((x) << VIVS_PE_LOGIC_OP_OP__SHIFT) & VIVS_PE_LOGIC_OP_OP__MASK)
#define VIVS_PE_LOGIC_OP_OP_MASK 0x00000010
#define VIVS_PE_DITHER(i0) (0x000014a8 + 0x4*(i0))
diff --git a/native/include/etna/state_hi.xml.h b/native/include/etna/state_hi.xml.h
index 577cc22..deab7dd 100644
--- a/native/include/etna/state_hi.xml.h
+++ b/native/include/etna/state_hi.xml.h
@@ -8,11 +8,11 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/common.xml ( 15637 bytes, from 2013-02-01 10:14:07)
+- /home/orion/projects/etna_viv/rnndb/state.xml ( 14962 bytes, from 2013-02-02 08:24:22)
+- /home/orion/projects/etna_viv/rnndb/common.xml ( 15601 bytes, from 2013-02-01 12:03:20)
- /home/orion/projects/etna_viv/rnndb/state_hi.xml ( 11825 bytes, from 2013-02-01 10:14:08)
- /home/orion/projects/etna_viv/rnndb/state_2d.xml ( 30577 bytes, from 2013-02-01 10:02:25)
-- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48941 bytes, from 2013-01-31 20:55:33)
+- /home/orion/projects/etna_viv/rnndb/state_3d.xml ( 48960 bytes, from 2013-02-02 16:37:28)
Copyright (C) 2013
*/
diff --git a/native/lib/etna_context_cmd.h b/native/lib/etna_context_cmd.h
index 97c3e8c..0520cba 100644
--- a/native/lib/etna_context_cmd.h
+++ b/native/lib/etna_context_cmd.h
@@ -5,7 +5,7 @@ typedef struct
} address_index_t;
/* global state map */
-address_index_t contextbuf_addr[] = {
+static address_index_t contextbuf_addr[] = {
{0x2e9, 0x00600}, /* FE.VERTEX_ELEMENT_CONFIG[0] */
{0x2ea, 0x00604}, /* FE.VERTEX_ELEMENT_CONFIG[1] */
{0x2eb, 0x00608}, /* FE.VERTEX_ELEMENT_CONFIG[2] */
@@ -4073,7 +4073,7 @@ address_index_t contextbuf_addr[] = {
{0xefe, 0x073FC} /* PS.UNIFORMS[255] */
};
-uint32_t contextbuf[] = {
+static uint32_t contextbuf[] = {
0x08010e03, /* LOAD_STATE (1) Base: 0x0380C Size: 1 Fixp: 0 */
0x00000007, /* GLOBAL.FLUSH_CACHE := DEPTH=1,COLOR=1,3D_TEXTURE=1,2D=0,UNK4=0,SHADER_L1=0,SHADER_L2=0 */
0x08010e02, /* LOAD_STATE (1) Base: 0x03808 Size: 1 Fixp: 0 */
diff --git a/native/lib/etna_tex.c b/native/lib/etna_tex.c
new file mode 100644
index 0000000..1cbd83c
--- /dev/null
+++ b/native/lib/etna_tex.c
@@ -0,0 +1,36 @@
+#include "etna_tex.h"
+
+#include <stdint.h>
+
+void etna_texture_tile(void *dest, void *src, unsigned width, unsigned height, unsigned src_stride, unsigned elmtsize)
+{
+#define TEX_TILE_WIDTH (4)
+#define TEX_TILE_HEIGHT (4)
+#define TEX_TILE_WORDS (TEX_TILE_WIDTH*TEX_TILE_HEIGHT)
+ unsigned ytiles = height / TEX_TILE_HEIGHT;
+ unsigned xtiles = width / TEX_TILE_WIDTH;
+ unsigned dst_stride = xtiles * TEX_TILE_WORDS;
+ if(elmtsize == 4)
+ {
+ src_stride >>= 2;
+
+ for(unsigned ty=0; ty<ytiles; ++ty)
+ {
+ for(unsigned tx=0; tx<xtiles; ++tx)
+ {
+ unsigned ofs = ty * dst_stride + tx * TEX_TILE_WORDS;
+ for(unsigned y=0; y<TEX_TILE_HEIGHT; ++y)
+ {
+ for(unsigned x=0; x<TEX_TILE_WIDTH; ++x)
+ {
+ unsigned srcy = ty*TEX_TILE_HEIGHT + y;
+ unsigned srcx = tx*TEX_TILE_WIDTH + x;
+ ((uint32_t*)dest)[ofs] = ((uint32_t*)src)[srcy*src_stride+srcx];
+ ofs += 1;
+ }
+ }
+ }
+ }
+ }
+}
+
diff --git a/native/lib/etna_tex.h b/native/lib/etna_tex.h
new file mode 100644
index 0000000..62f4b58
--- /dev/null
+++ b/native/lib/etna_tex.h
@@ -0,0 +1,6 @@
+#ifndef H_ETNA_TEX
+
+void etna_texture_tile(void *dest, void *src, unsigned width, unsigned height, unsigned src_stride, unsigned elmtsize);
+
+#endif
+
diff --git a/native/replay/Makefile b/native/replay/Makefile
index 89f5f02..0e49b74 100644
--- a/native/replay/Makefile
+++ b/native/replay/Makefile
@@ -9,6 +9,7 @@ LDFLAGS += -lm
TARGETS = cube cube_companion cube_etna ps_sandbox_etna etna_test reset viv_info cube_etna2
COMPANION_OBJS = ../resources/companion_array.o ../resources/companion_mesh.o ../resources/companion_texture.o
+ETNA_OBJS = ../lib/viv.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_fb.o ../lib/etna_mem.o ../lib/etna_bswap.o ../lib/etna_tex.o
all: $(TARGETS)
@@ -25,13 +26,13 @@ cube_companion: cube_companion.o ../lib/write_bmp.o ../lib/viv.o $(COMPANION_OBJ
cube_etna: cube_etna.o ../lib/write_bmp.o ../lib/viv.o ../lib/esTransform.o
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
-cube_etna2: cube_etna2.o ../lib/write_bmp.o ../lib/viv.o ../lib/esTransform.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_mem.o
+cube_etna2: cube_etna2.o ../lib/write_bmp.o ../lib/esTransform.o $(ETNA_OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
ps_sandbox_etna: ps_sandbox_etna.o ../lib/write_bmp.o ../lib/viv.o ../lib/esTransform.o
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
-etna_test: etna_test.o ../lib/write_bmp.o ../lib/viv.o ../lib/esTransform.o ../lib/etna.o ../lib/etna_rs.o ../lib/etna_mem.o
+etna_test: etna_test.o ../lib/write_bmp.o ../lib/esTransform.o $(ETNA_OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
reset: reset.o ../lib/viv.o
diff --git a/native/replay/cube_etna.c b/native/replay/cube_etna.c
index b1dda06..20d9e20 100644
--- a/native/replay/cube_etna.c
+++ b/native/replay/cube_etna.c
@@ -543,7 +543,7 @@ int main(int argc, char **argv)
VIV_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0));
etna_set_state(cmdPtr, VIVS_PE_ALPHA_CONFIG, /* can & all these together */
VIV_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
- VIV_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0));
+ VIV_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0));
etna_set_state(cmdPtr, VIVS_PE_ALPHA_CONFIG,
VIV_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
VIV_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE));
diff --git a/native/replay/cube_etna2.c b/native/replay/cube_etna2.c
index 89c21fb..ce4756b 100644
--- a/native/replay/cube_etna2.c
+++ b/native/replay/cube_etna2.c
@@ -284,7 +284,7 @@ int main(int argc, char **argv)
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0));
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
- ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) &
+ ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
diff --git a/native/replay/etna_test.c b/native/replay/etna_test.c
index 4bb7c9b..e5117b2 100644
--- a/native/replay/etna_test.c
+++ b/native/replay/etna_test.c
@@ -154,7 +154,7 @@ int main(int argc, char **argv)
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0));
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
- ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) &
+ ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
diff --git a/native/replay/ps_sandbox_etna.c b/native/replay/ps_sandbox_etna.c
index 5af1541..c7d9739 100644
--- a/native/replay/ps_sandbox_etna.c
+++ b/native/replay/ps_sandbox_etna.c
@@ -436,7 +436,7 @@ int main(int argc, char **argv)
VIV_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0));
etna_set_state(cmdPtr, VIVS_PE_ALPHA_CONFIG, /* can & all these together */
VIV_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
- VIV_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0));
+ VIV_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0));
etna_set_state(cmdPtr, VIVS_PE_ALPHA_CONFIG,
VIV_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
VIV_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE));
diff --git a/rnndb/common.xml b/rnndb/common.xml
new file mode 100644
index 0000000..4ca36c6
--- /dev/null
+++ b/rnndb/common.xml
@@ -0,0 +1,260 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Copyright (c) 2012-2013 The Etnaviv Project
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sub license,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice (including the
+ next paragraph) shall be included in all copies or substantial portions
+ of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+-->
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+<!-- Shared enums and type definitions.
+ -->
+ <enum name="ENABLE_DISABLE" inline="yes">
+ <!-- Generic type for functionality that can be enabled/disabled, it can be somewhat clearer than a
+ boolean (RNN default type for 1-bit values) in some cases.
+ -->
+ <value value="0" name="DISABLE"/>
+ <value value="1" name="ENABLE"/>
+ </enum>
+ <enum name="PIPE_ID">
+ <value value="0" name="PIPE_3D"/>
+ <value value="1" name="PIPE_2D"/> <!-- DE only -->
+ </enum>
+ <enum name="SYNC_RECIPIENT" brief="Synchronization source/destination">
+ <doc>This is used for synchronization primitives, for example for semaphores and stalling</doc>
+ <value value="1" name="FE" brief="Front End"/>
+ <value value="5" name="RA" brief="Raster"/>
+ <value value="7" name="PE" brief="Pixel Engine"/>
+ <value value="11" name="DE" brief="Drawing Engine"/>
+ </enum>
+ <enum name="ENDIAN_MODE" brief="Byte swap configuration">
+ <value value="0" name="NO_SWAP" brief="No endian swap"/>
+ <value value="1" name="SWAP_16" brief="Swap per 16 bit unit"/>
+ <value value="2" name="SWAP_32" brief="Swap per 32 bit unit"/>
+ </enum>
+ <bitset name="RGBA_BITS" brief="RGBA bits">
+ <bitfield pos="0" name="R"/>
+ <bitfield pos="1" name="G"/>
+ <bitfield pos="2" name="B"/>
+ <bitfield pos="3" name="A"/>
+ </bitset>
+
+ <enum name="chipModel">
+ <value value="0x0300" name="GC300"/> <!-- 2D graphics -->
+ <value value="0x0320" name="GC320"/> <!-- 2D graphics + Compose engine -->
+ <value value="0x0350" name="GC350"/> <!-- OpenVG -->
+ <value value="0x0355" name="GC355"/> <!-- OpenVG -->
+ <value value="0x0400" name="GC400"/> <!-- 3D graphics, 1 core, according to Vivante it is "the smallest OpenGL ES 2.0 compliant GPU available today" -->
+ <value value="0x0410" name="GC410"/>
+ <value value="0x0420" name="GC420"/>
+ <value value="0x0450" name="GC450"/>
+ <value value="0x0500" name="GC500"/>
+ <value value="0x0530" name="GC530"/>
+ <value value="0x0600" name="GC600"/>
+ <value value="0x0700" name="GC700"/>
+ <value value="0x0800" name="GC800"/> <!-- 3D graphics, 1 core -->
+ <value value="0x0860" name="GC860"/>
+ <value value="0x0880" name="GC880"/>
+ <value value="0x1000" name="GC1000"/> <!-- 3D graphics, 2 cores -->
+ <value value="0x2000" name="GC2000"/> <!-- 3D graphics, 4 cores -->
+ <value value="0x2100" name="GC2100"/>
+ <value value="0x4000" name="GC4000"/> <!-- 3D graphics, 8 cores -->
+ </enum>
+ <bitset name="chipFeatures">
+ <bitfield pos="0" name="FAST_CLEAR" brief="Fast clear available"/>
+ <bitfield pos="1" name="SPECIAL_ANTI_ALIASING" brief="Special AA (FSAA)"/>
+ <bitfield pos="2" name="PIPE_3D" brief="3D engine is present"/>
+ <bitfield pos="3" name="DXT_TEXTURE_COMPRESSION" brief="DXT texture compression"/>
+ <bitfield pos="4" name="DEBUG_MODE" brief="Debug registers present"/>
+ <bitfield pos="5" name="Z_COMPRESSION" brief="Depth and color compression"/>
+ <bitfield pos="6" name="YUV420_SCALER" brief="YUV 4:2:0 support in filter blit"/>
+ <bitfield pos="7" name="MSAA" brief="Multi Sample Anti-Aliasing"/>
+ <bitfield pos="8" name="DC" brief="Display controller"/>
+ <bitfield pos="9" name="PIPE_2D" brief="2D engine is present"/>
+ <bitfield pos="10" name="ETC1_TEXTURE_COMPRESSION" brief="Ericcson texture compression"/>
+ <bitfield pos="11" name="FAST_SCALER" brief="HD scaler present"/>
+ <bitfield pos="12" name="HIGH_DYNAMIC_RANGE" brief="High dynamic range support"/>
+ <bitfield pos="13" name="YUV420_TILER" brief="YUV 4:2:0 tiler is available"/>
+ <bitfield pos="14" name="MODULE_CG" brief="Second-level clock gating available"/>
+ <bitfield pos="15" name="MIN_AREA" brief="Optimized for minimum area"/>
+ <bitfield pos="16" name="NO_EARLY_Z" brief="No early-Z"/>
+ <bitfield pos="17" name="NO_422_TEXTURE" brief="No 4:2:2 YUV texture input format"/>
+ <bitfield pos="18" name="BUFFER_INTERLEAVING" brief="Supports interleaving depth and color buffers"/>
+ <bitfield pos="19" name="BYTE_WRITE_2D" brief="Supports byte write in 2D"/>
+ <bitfield pos="20" name="NO_SCALER" brief="No 2D scaler"/>
+ <bitfield pos="21" name="YUY2_AVERAGING" brief="YUY2 averaging support in resolve"/>
+ <bitfield pos="22" name="HALF_PE_CACHE" brief="PE cache is half"/>
+ <bitfield pos="23" name="HALF_TX_CACHE" brief="TX cache is half"/>
+ <bitfield pos="24" name="YUY2_RENDER_TARGET" brief="YUY2 support in PE and YUY2 to RGB conversion in resolve"/>
+ <bitfield pos="25" name="MEM32" brief="32 bit memory address support"/>
+ <bitfield pos="26" name="PIPE_VG" brief="OpenVG engine is present"/>
+ <bitfield pos="27" name="VGTS" brief="VG tesselator is present"/>
+ <bitfield pos="28" name="FE20" brief="FE 2.0 is present"/>
+ <bitfield pos="29" name="BYTE_WRITE_3D" brief="3D PE has byte write capability"/>
+ <bitfield pos="30" name="RS_YUV_TARGET" brief="Supports resolving into YUV target"/>
+ <bitfield pos="31" name="32_BIT_INDICES" brief="32 bit indices can be used with indexed drawing"/>
+ </bitset>
+ <bitset name="chipMinorFeatures0">
+ <bitfield pos="0" name="FLIP_Y" brief="Y flipping capability is added to resolve"/>
+ <bitfield pos="1" name="DUAL_RETURN_BUS" brief="Dual Return Bus from HI to clients"/>
+ <bitfield pos="2" name="ENDIANNESS_CONFIG" brief="Configurable endianness support"/>
+ <bitfield pos="3" name="TEXTURE_8K" brief="8Kx8K texture support"/>
+ <bitfield pos="4" name="CORRECT_TEXTURE_CONVERTER" brief="Driver hack is not needed (?)"/>
+ <bitfield pos="5" name="SPECIAL_MSAA_LOD" brief="Special LOD calculation when MSAA is on"/>
+ <bitfield pos="6" name="FAST_CLEAR_FLUSH" brief="Proper flush is done in fast clear cache"/>
+ <bitfield pos="7" name="2DPE20" brief="Pixel Engine 2.0"/>
+ <bitfield pos="8" name="CORRECT_AUTO_DISABLE" brief="Reserved"/>
+ <bitfield pos="9" name="RENDERTARGET_8K" brief="8Kx8K render target support"/>
+ <bitfield pos="10" name="2BITPERTILE" brief="Two status bits per tile (instead of four)"/>
+ <bitfield pos="11" name="SEPARATE_TILE_STATUS_WHEN_INTERLEAVED" brief="Use 2 separate tile status buffers in interleaved mode"/>
+ <bitfield pos="12" name="SUPER_TILED" brief="32x32 super tile is available"/>
+ <bitfield pos="13" name="VG_20" brief="Major updates to VG pipe (TS buffer tiling, state masking)"/>
+ <bitfield pos="14" name="TS_EXTENDED_COMMANDS" brief="New commands added to the VG tessellator"/>
+ <bitfield pos="15" name="COMPRESSION_FIFO_FIXED"/>
+ <bitfield pos="16" name="HAS_SIGN_FLOOR_CEIL" brief="Has SIGN, FLOOR and CEIL shader instructions"/>
+ <bitfield pos="17" name="VG_FILTER" brief="VG filter is available"/>
+ <bitfield pos="18" name="VG_21" brief="Minor updates to VG pipe (Event generation from VG, TS, PE, tiled image support)"/>
+ <bitfield pos="19" name="SHADER_HAS_W" brief="W is sent to SH from RA"/>
+ <bitfield pos="20" name="HAS_SQRT_TRIG" brief="Has SQRT, SIN, COS instructions"/>
+ <bitfield pos="21" name="MORE_MINOR_FEATURES" brief="Chip has CHIP_MINOR_FEATURE_(1|2|3)">
+ <doc>Also, in the shader unavailable registers will return 0</doc>
+ </bitfield>
+ <bitfield pos="22" name="MC20" brief="New style MC with separate paths for color and depth"/>
+ <bitfield pos="23" name="MSAA_SIDEBAND" brief="Put the MSAA data into sideband fifo"/>
+ <bitfield pos="24" name="BUG_FIXES0"/>
+ <bitfield pos="25" name="VAA" brief="Coverage anti-aliasing"/>
+ <bitfield pos="26" name="BYPASS_IN_MSAA" brief="Shader supports bypass mode when MSAA is enabled"/>
+ <bitfield pos="27" name="HZ" brief="Hierarchical Z-buffer"/>
+ <bitfield pos="28" name="NEW_TEXTURE" brief="New texture unit is available"/>
+ <bitfield pos="29" name="2D_A8_TARGET" brief="2D engine supports A8 target"/>
+ <bitfield pos="30" name="CORRECT_STENCIL" brief="Correct stencil behavior in depth only"/>
+ <bitfield pos="31" name="ENHANCE_VR" brief="Enhance video rasterizer"/>
+ </bitset>
+ <bitset name="chipMinorFeatures1">
+ <bitfield pos="0" name="RSUV_SWIZZLE" brief="Resolve UV swizzle"/>
+ <bitfield pos="1" name="V2_COMPRESSION" brief="V2 compression"/>
+ <bitfield pos="2" name="VG_DOUBLE_BUFFER" brief="Double buffering support for VG (second TS-->VG semaphore is present)"/>
+ <bitfield pos="3" name="EXTRA_EVENT_STATES"/>
+ <bitfield pos="4" name="NO_STRIPING_NEEDED"/>
+ <bitfield pos="5" name="TEXTURE_STRIDE" brief="Texture has stride and memory addressing"/>
+ <bitfield pos="6" name="BUG_FIXES3"/>
+ <bitfield pos="7" name="AUTO_DISABLE"/>
+ <bitfield pos="8" name="AUTO_RESTART_TS"/>
+ <bitfield pos="9" name="DISABLE_PE_GATING"/>
+ <bitfield pos="10" name="L2_WINDOWING"/>
+ <bitfield pos="11" name="HALF_FLOAT" brief="Supports 16-bit floating point type"/>
+ <bitfield pos="12" name="PIXEL_DITHER"/>
+ <bitfield pos="13" name="TWO_STENCIL_REFERENCE"/>
+ <bitfield pos="14" name="EXTENDED_PIXEL_FORMAT"/>
+ <bitfield pos="15" name="CORRECT_MIN_MAX_DEPTH" brief="EEZ and HZ are correct"/>
+ <bitfield pos="16" name="2D_DITHER" brief="2D dither and filter+alpha available"/>
+ <bitfield pos="17" name="BUG_FIXES5"/>
+ <bitfield pos="18" name="NEW_2D" brief="Mirror extension available"/>
+ <bitfield pos="19" name="NEW_FP" brief="New floating point arithmetic"/>
+ <bitfield pos="20" name="TEXTURE_ALIGN_4" brief="Textures can be aligned to 4 instead of 16"/>
+ <bitfield pos="21" name="NON_POWER_OF_TWO" brief="Non power-of-two texture support"/>
+ <bitfield pos="22" name="LINEAR_TEXTURE_SUPPORT"/>
+ <bitfield pos="23" name="HALTI0" brief="Various features related to texturing and vertex processing">
+ <doc>
+ - Anisotropic texture filtering
+ - 3D texture support
+ - Texture array support
+ - GL_(INT|UNSIGNED)_10_10_10_2_OES texture / vertex support
+ - 16 attr per vertex i.s.o. 10, and 12 varyings i.s.o. 8
+ </doc>
+ </bitfield>
+ <bitfield pos="24" name="CORRECT_OVERFLOW_VG"/>
+ <bitfield pos="25" name="NEGATIVE_LOG_FIX"/>
+ <bitfield pos="26" name="RESOLVE_OFFSET"/>
+ <bitfield pos="27" name="OK_TO_GATE_AXI_CLOCK"/>
+ <bitfield pos="28" name="MMU_VERSION"/>
+ <bitfield pos="29" name="WIDE_LINE"/>
+ <bitfield pos="30" name="BUG_FIXES6"/>
+ <bitfield pos="31" name="FC_FLUSH_STALL"/>
+ </bitset>
+ <bitset name="chipMinorFeatures2">
+ <bitfield pos="0" name="LINE_LOOP"/>
+ <bitfield pos="1" name="LOGIC_OP"/>
+ <bitfield pos="2" name="UNK2"/>
+ <bitfield pos="3" name="SUPERTILED_TEXTURE"/>
+ <bitfield pos="4" name="UNK4"/>
+ <bitfield pos="5" name="RECT_PRIMITIVE"/>
+ <bitfield pos="6" name="COMPOSITION" brief="Compose engine present"/>
+ <bitfield pos="7" name="CORRECT_AUTO_DISABLE_COUNT"/>
+ <bitfield pos="8" name="UNK8"/>
+ <bitfield pos="9" name="UNK9"/>
+ <bitfield pos="10" name="UNK10"/>
+ <bitfield pos="11" name="SAMPLERBASE_16" brief="New texture block exists (0x10000 - 0x11000)"/>
+ <bitfield pos="12" name="UNK12"/>
+ <bitfield pos="13" name="UNK13"/>
+ <bitfield pos="14" name="UNK14"/>
+ <bitfield pos="15" name="EXTRA_TEXTURE_STATE" brief="Extra texture state (0x12000)"/>
+ <bitfield pos="16" name="FULL_DIRECTFB"/>
+ <bitfield pos="17" name="2D_TILING" brief="2D tiling and YUV blit"/>
+ <bitfield pos="18" name="THREAD_WALKER_IN_PS"/>
+ <bitfield pos="19" name="TILE_FILLER"/>
+ <bitfield pos="20" name="UNK20"/>
+ <bitfield pos="21" name="2D_MULTI_SOURCE_BLIT"/>
+ <bitfield pos="22" name="UNK22"/>
+ <bitfield pos="23" name="UNK23"/>
+ <bitfield pos="24" name="UNK24"/>
+ <bitfield pos="25" name="MIXED_STREAMS"/>
+ <bitfield pos="26" name="2D_420_L2CACHE"/>
+ <bitfield pos="27" name="UNK27"/>
+ <bitfield pos="28" name="2D_NO_INDEX8_BRUSH"/>
+ <bitfield pos="29" name="TEXTURE_TILED_READ" brief="Tiled read also available with COMPOSITION"/>
+ <bitfield pos="30" name="UNK30"/>
+ <bitfield pos="31" name="UNK31"/>
+ </bitset>
+ <bitset name="chipMinorFeatures3"> <!-- Only for newer hardware/drivers (gc1000+?) -->
+ <bitfield pos="0" name="ROTATION_STALL_FIX"/>
+ <bitfield pos="1" name="UNK1"/>
+ <bitfield pos="2" name="2D_MULTI_SOURCE_BLT_EX" brief="8 instead of 4 multisource blit sources"/>
+ <bitfield pos="3" name="UNK3"/>
+ <bitfield pos="4" name="UNK4"/>
+ <bitfield pos="5" name="UNK5"/>
+ <bitfield pos="6" name="UNK6"/>
+ <bitfield pos="7" name="UNK7"/>
+ <bitfield pos="8" name="UNK8"/>
+ <bitfield pos="9" name="UNK9"/>
+ <bitfield pos="10" name="BUG_FIXES10"/>
+ <bitfield pos="11" name="UNK11"/>
+ <bitfield pos="12" name="BUG_FIXES11"/>
+ <bitfield pos="13" name="UNK13"/>
+ <bitfield pos="14" name="UNK14"/>
+ <bitfield pos="15" name="UNK15"/>
+ <bitfield pos="16" name="UNK16"/>
+ <bitfield pos="17" name="UNK17"/>
+ <bitfield pos="18" name="UNK18"/>
+ <bitfield pos="19" name="UNK19"/>
+ <bitfield pos="20" name="UNK20"/>
+ <bitfield pos="21" name="UNK21"/>
+ <bitfield pos="22" name="UNK22"/>
+ <bitfield pos="23" name="UNK23"/>
+ <bitfield pos="24" name="UNK24"/>
+ <bitfield pos="25" name="UNK25"/>
+ <bitfield pos="26" name="UNK26"/>
+ <bitfield pos="27" name="UNK27"/>
+ <bitfield pos="28" name="UNK28"/>
+ <bitfield pos="29" name="UNK29"/>
+ <bitfield pos="30" name="UNK30"/>
+ <bitfield pos="31" name="UNK31"/>
+ </bitset>
+</database>
+
diff --git a/rnndb/state.xml b/rnndb/state.xml
index 258f35b..0633f63 100644
--- a/rnndb/state.xml
+++ b/rnndb/state.xml
@@ -179,7 +179,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<bitfield pos="5" name="SHADER_L1"/>
<bitfield pos="6" name="SHADER_L2"/>
</reg32>
- <reg32 offset="0x03810" name="FLUSH_MMU" brief="Flush the virtual addrses lookup cache inside the MC">
+ <reg32 offset="0x03810" name="FLUSH_MMU" brief="Flush the virtual address lookup cache inside the MC">
<bitfield pos="0" name="FLUSH_FEMMU" brief="Flush the FE address translation caches"/>
<bitfield pos="1" name="FLUSH_PEMMU" brief="Flush the PE render target address translation caches"/>
</reg32>
diff --git a/rnndb/state_3d.xml b/rnndb/state_3d.xml
new file mode 100644
index 0000000..1cebdaa
--- /dev/null
+++ b/rnndb/state_3d.xml
@@ -0,0 +1,821 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Copyright (c) 2012-2013 The Etnaviv Project
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sub license,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice (including the
+ next paragraph) shall be included in all copies or substantial portions
+ of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+-->
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+<!-- Vivante GCxxxx render states and registers overview:
+ PIPE_3D (3D rendering) state. Based on reverse engineering, guesswork and experimentation.
+ -->
+<domain name="VIVS" brief="GPU state">
+ <enum name="COMPARE_FUNC" brief="Compare function (for glStencilFunc and glDepthFunc)">
+ <!-- Either a coincidence or due to shared roots in DirectX: same enum as Gallium3D PIPE_FUNC -->
+ <value value="0" name="NEVER"/>
+ <value value="1" name="LESS"/>
+ <value value="2" name="EQUAL"/>
+ <value value="3" name="LEQUAL"/>
+ <value value="4" name="GREATER"/>
+ <value value="5" name="NOTEQUAL"/>
+ <value value="6" name="GEQUAL"/>
+ <value value="7" name="ALWAYS"/>
+ </enum>
+ <enum name="STENCIL_OP" brief="Stencil operation">
+ <value value="0" name="KEEP" brief="Keeps the current value"/>
+ <value value="1" name="ZERO" brief="Sets the stencil buffer value to 0"/>
+ <value value="2" name="REPLACE" brief="Sets the stencil value to ref"/>
+ <value value="3" name="INCR" brief="Increments stencil buffer value, clamps to max"/>
+ <value value="4" name="DECR" brief="Descrements stencil buffer value, clamps to min"/>
+ <value value="5" name="INVERT" brief="Bitwise inverts the current stencil buffer value"/>
+ <value value="6" name="INCR_WRAP" brief="Increments stencil buffer value, wraps around"/>
+ <value value="7" name="DECR_WRAP" brief="Decrements stencil buffer value, wraps around"/>
+ </enum>
+ <enum name="BLEND_EQ" brief="Blend equation">
+ <doc>determines how pixel blending combines source and destination</doc>
+ <value value="0" name="ADD"/>
+ <value value="1" name="SUBTRACT"/>
+ <value value="2" name="REVERSE_SUBTRACT"/>
+ <value value="3" name="MIN"/>
+ <value value="4" name="MAX"/>
+ </enum>
+ <enum name="BLEND_FUNC" brief="glBlendFunc">
+ <value value="0" name="ZERO"/>
+ <value value="1" name="ONE"/>
+ <value value="2" name="SRC_COLOR"/>
+ <value value="3" name="ONE_MINUS_SRC_COLOR"/>
+ <value value="4" name="SRC_ALPHA"/>
+ <value value="5" name="ONE_MINUS_SRC_ALPHA"/>
+ <value value="6" name="DST_ALPHA"/>
+ <value value="7" name="ONE_MINUS_DST_ALPHA"/>
+ <value value="8" name="DST_COLOR"/>
+ <value value="9" name="ONE_MINUS_DST_COLOR"/>
+ <value value="10" name="SRC_ALPHA_SATURATE"/>
+ <value value="11" name="CONSTANT_ALPHA"/>
+ <value value="12" name="ONE_MINUS_CONSTANT_ALPHA"/>
+ <value value="13" name="CONSTANT_COLOR"/>
+ <value value="14" name="ONE_MINUS_CONSTANT_COLOR"/>
+ </enum>
+ <enum name="RS_FORMAT" brief="Resolve pixel format">
+ <value value="0" name="X4R4G4B4"/>
+ <value value="1" name="A4R4G4B4"/>
+ <value value="2" name="X1R5G5B5"/>
+ <value value="3" name="A1R5G5B5"/>
+ <value value="4" name="R5G6B5"/>
+ <value value="5" name="X8R8G8B8"/>
+ <value value="6" name="A8R8G8B8"/>
+ <value value="7" name="YUY2"/><!-- only supported with YUY2_AVERAGING -->
+ <!-- 8..15 do show color and don't result in GPU crashes directly, also they don't
+ seem to be direct aliases of 0..7, but it needs to be figured out if
+ they're useful or just alternative names for formats in range 0..7
+ -->
+ </enum>
+ <enum name="TEXTURE_FORMAT" brief="Texture format">
+ <!-- 0 read as all zeros -->
+ <value value="1" name="A8"/>
+ <value value="2" name="L8"/>
+ <value value="3" name="I8"/>
+ <value value="4" name="A8L8"/>
+ <value value="5" name="A4R4G4B4"/>
+ <value value="6" name="X4R4G4B4"/>
+ <value value="7" name="A8R8G8B8"/>
+ <value value="8" name="X8R8G8B8"/>
+ <value value="9" name="A8B8G8R8"/>
+ <value value="10" name="X8B8G8R8"/>
+ <value value="11" name="R5G6B5"/>
+ <value value="12" name="A1R5G5B5"/>
+ <value value="13" name="X1R5G5B5"/>
+ <value value="14" name="YUY2" brief="YUV 4:2:2"/>
+ <value value="15" name="UYVY" brief="YUV 4:2:2 (Alt macropixel ordering)"/>
+ <value value="16" name="D16"/>
+ <value value="17" name="D24S8"/>
+ <!-- 18 reads as all ones -->
+ <value value="19" name="DXT1" brief="S3 Block Compression 1">
+ <doc>DXT1: Unknown tiling.</doc>
+ </value>
+ <value value="20" name="DXT2_DXT3" brief="S3 Block Compression 2"/>
+ <value value="21" name="DXT4_DXT5" brief="S3 Block Compression 3">
+ <doc>DXT4/DXT5 compressed textures are stored untiled.</doc>
+ </value>
+ <!-- 22-29 read as all zeros -->
+ <value value="30" name="ETC1" brief="Ericsson Texture Compression">
+ <doc>ETC compressed textures are stored untiled.</doc>
+ </value>
+ <!-- 31 read as all zeros -->
+ </enum>
+ <enum name="TEXTURE_FORMAT_EXT" brief="Extended texture format">
+ <value value="0" name="NONE"/>
+ <value value="7" name="A16F" brief="16-bit fp alpha format" />
+ <value value="8" name="A16L16F" brief="16-bit fp alpha luminosity format" />
+ <value value="9" name="A16B16G16R16F" brief="16-bit fp rgba format" />
+ <value value="10" name="A32F" brief="32-bit fp alpha format" />
+ <value value="11" name="A32L32F" brief="32-bit fp alpha luminosity format" />
+ <value value="12" name="A2B10G10R10"/>
+ </enum>
+ <enum name="TEXTURE_FILTER">
+ <value value="0" name="NONE"/>
+ <value value="1" name="NEAREST"/>
+ <value value="2" name="LINEAR"/>
+ <value value="3" name="ANISOTROPIC"/><!-- Only supported if HALTI0 feature bit set -->
+ </enum>
+ <enum name="TEXTURE_TYPE">
+ <!-- 0 shows up as black -->
+ <!-- 1 crashes GPU -->
+ <value value="2" name="2D"/>
+ <!-- 3 crashes GPU -->
+ <!-- 4 crashes GPU -->
+ <value value="5" name="CUBE_MAP"/>
+ <!-- 6 crashes GPU -->
+ <!-- 7 crashes GPU -->
+ </enum>
+ <enum name="TEXTURE_WRAPMODE">
+ <value value="0" name="REPEAT"/>
+ <value value="1" name="MIRRORED_REPEAT"/>
+ <value value="2" name="CLAMP_TO_EDGE"/>
+ <!-- 3 seems to be same as REPEAT -->
+ </enum>
+ <enum name="TEXTURE_FACE">
+ <doc>Offset into texture memory for cube map face</doc>
+ <value value="0" name="POS_X"/>
+ <value value="1" name="NEG_X"/>
+ <value value="2" name="POS_Y"/>
+ <value value="3" name="NEG_Y"/>
+ <value value="4" name="POS_Z"/>
+ <value value="5" name="NEG_Z"/>
+ </enum>
+ <enum name="TEXTURE_SWIZZLE">
+ <!-- Matches Gallium3D PIPE_SWIZZLE -->
+ <value value="0" name="RED"/>
+ <value value="1" name="GREEN"/>
+ <value value="2" name="BLUE"/>
+ <value value="3" name="ALPHA"/>
+ <value value="4" name="ZERO"/>
+ <value value="5" name="ONE"/>
+ </enum>
+ <enum name="LOGIC_OP" brief="LogicOp">
+ <value value="0" name="CLEAR"/>
+ <value value="1" name="NOR"/>
+ <value value="2" name="AND_INVERTED"/>
+ <value value="3" name="COPY_INVERTED"/>
+ <value value="4" name="AND_REVERSE"/>
+ <value value="5" name="INVERT"/>
+ <value value="6" name="XOR"/>
+ <value value="7" name="NAND"/>
+ <value value="8" name="AND"/>
+ <value value="9" name="EQUIV"/>
+ <value value="10" name="NOOP"/>
+ <value value="11" name="OR_INVERTED"/>
+ <value value="12" name="COPY"/> <!-- Default -->
+ <value value="13" name="OR_REVERSE"/>
+ <value value="14" name="OR"/>
+ <value value="15" name="SET"/>
+ </enum>
+
+ <stripe name="VS" brief="Vertex shader states">
+ <doc>The vertex shader to be used for 3D rendering is configured here.</doc>
+ <reg32 offset="0x00800" name="END_PC" value="0x00000000" brief="End instruction number">
+ <doc>index of last instruction + 1</doc>
+ </reg32>
+ <reg32 offset="0x00804" name="OUTPUT_COUNT" value="0x00000000" type="uint" brief="Number of VS outputs"/>
+ <reg32 offset="0x00808" name="INPUT_COUNT" value="0x00000000">
+ <bitfield high="3" low="0" name="COUNT" type="uint" brief="Number of VS inputs"/>
+ <bitfield high="12" low="8" name="UNK8" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0080C" name="TEMP_REGISTER_CONTROL" brief="Temporary register control" value="0x00000000">
+ <bitfield high="5" low="0" name="NUM_TEMPS" type="uint" brief="Number of temporary registers"/>
+ </reg32>
+ <reg32 offset="0x00810" name="OUTPUT" value="0x00000000" brief="Output routing" length="4" stride="4">
+ <doc>
+ Each bitfield (up to 16 in total) contains a temporary register number that
+ is used as output at the end of the shader for that varying.
+ </doc>
+ <bitfield high="7" low="0" name="O0" type="uint"/>
+ <bitfield high="15" low="8" name="O1" type="uint"/>
+ <bitfield high="23" low="16" name="O2" type="uint"/>
+ <bitfield high="31" low="24" name="O3" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00820" name="INPUT" value="0x00000000" brief="Input routing" length="4" stride="4">
+ <doc>
+ Each bitfield (up to 16 in total) contains a temporary register number that
+ is assigned the input for that attribute at the beginning of shader execution.
+ </doc>
+ <bitfield high="7" low="0" name="I0" type="uint"/>
+ <bitfield high="15" low="8" name="I1" type="uint"/>
+ <bitfield high="23" low="16" name="I2" type="uint"/>
+ <bitfield high="31" low="24" name="I3" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00830" name="LOAD_BALANCING" value="0x00000000"/>
+ <reg32 offset="0x00834" name="PERF_COUNTER" brief="Performance counter control"/>
+ <reg32 offset="0x00838" name="START_PC" value="0x00000000"/>
+ <reg32 offset="0x00850" name="UNK00850" value="0x000003e8"/>
+ <reg32 offset="0x00854" name="UNK00854" value="0x00000100"/>
+ <reg32 offset="0x00858" name="UNK00858" value="0x00001005"/>
+ <reg32 offset="0x04000" name="INST_MEM" value="0x00000000" length="1024" stride="4"> <!-- instructionCount <= 256 -->
+ <!-- length="instructionCount * 4" -->
+ </reg32>
+ <reg32 offset="0x05000" name="UNIFORMS" value="0x00000000" length="1024" stride="4">
+ <!-- length="vertexUniforms * 4" -->
+ </reg32>
+ </stripe>
+
+ <stripe name="THREAD_WALKER" brief="Thread walker states">
+ <doc>The thread walker drives shaders in a predefined grid for GPGPU computing (OpenCL).
+ These states are not used for normal rendering.</doc>
+ <reg32 offset="0x00900" name="UNK00900" value="0x00000000"/>
+ <reg32 offset="0x00904" name="UNK00904" value="0x00000000"/>
+ <reg32 offset="0x00908" name="UNK00908" value="0x00000000"/>
+ <reg32 offset="0x0090C" name="UNK0090C" value="0x00000000"/>
+ <reg32 offset="0x00910" name="UNK00910" value="0x00000000"/>
+ <reg32 offset="0x00914" name="UNK00914" value="0x00000000"/>
+ <reg32 offset="0x00918" name="UNK00918" value="0x00000000"/>
+ <reg32 offset="0x0091C" name="UNK0091C" value="0x00000000"/>
+ <reg32 offset="0x00920" name="KICKER" brief="Start thread walker">
+ <doc>Write some value to this register to kick off thread walker</doc>
+ </reg32>
+ <reg32 offset="0x00924" name="UNK00924" value="0x00000000"/>
+ </stripe>
+
+ <stripe name="PA" brief="Primitive assembly states">
+ <doc>Primitive assembly assembles primitives (tris, quads, lines, points etc) from vertices for 3D rendering.
+ Viewport scaling, line width and point size is configured here.</doc>
+ <reg32 offset="0x00A00" name="VIEWPORT_SCALE_X" value="0x00000000" type="fixedp"/>
+ <reg32 offset="0x00A04" name="VIEWPORT_SCALE_Y" value="0x00000000" type="fixedp"/>
+ <reg32 offset="0x00A08" name="VIEWPORT_SCALE_Z" value="0x00000000" type="float"/>
+ <reg32 offset="0x00A0C" name="VIEWPORT_OFFSET_X" value="0x00000000" type="fixedp"/>
+ <reg32 offset="0x00A10" name="VIEWPORT_OFFSET_Y" value="0x00000000" type="fixedp"/>
+ <reg32 offset="0x00A14" name="VIEWPORT_OFFSET_Z" value="0x00000000" type="float"/>
+ <reg32 offset="0x00A18" name="LINE_WIDTH" value="0x00000000"/>
+ <reg32 offset="0x00A1C" name="POINT_SIZE" value="0x00000000"/>
+ <reg32 offset="0x00A28" name="SYSTEM_MODE" value="0x00000000"> <!-- D3D/OpenGL switch -->
+ <doc>0x11 for OpenGL</doc>
+ </reg32>
+ <reg32 offset="0x00A2C" name="W_CLIP_LIMIT" value="0x00000000"/>
+ <reg32 offset="0x00A30" name="ATTRIBUTE_ELEMENT_COUNT" value="0x00000000">
+ <bitfield high="7" low="0" name="UNK0"/>
+ <bitfield high="15" low="8" name="COUNT"/>
+ </reg32>
+ <reg32 offset="0x00A34" name="CONFIG" value="0x00000000" brief="Primitive assembly state flags" masked="yes">
+ <doc>
+ These can be set either per group of bits, or all at once, by using masking flags.
+ Each group of state flags has a masking flag that prevents overwriting the flags in that group.
+ </doc>
+ <bitfield pos="2" name="POINT_SIZE_ENABLE" brief="Enable point size"/>
+ <bitfield pos="3" name="POINT_SIZE_ENABLE_MASK"/>
+ <bitfield pos="4" name="POINT_SPRITE_ENABLE" brief="Enable point sprite"/>
+ <bitfield pos="5" name="POINT_SPRITE_ENABLE_MASK"/>
+ <bitfield high="9" low="8" name="CULL_FACE_MODE">
+ <value value="0" name="OFF" brief="Disable face culling"/>
+ <value value="1" name="CW" brief="Orientation of front-facing polygons is clockwise"/>
+ <value value="2" name="CCW" brief="Orientation of front-facing polygons is counter-clockwise"/>
+ </bitfield>
+ <bitfield pos="10" name="CULL_FACE_MODE_MASK"/>
+ <bitfield high="13" low="12" name="FILL_MODE">
+ <value value="0" name="POINT"/>
+ <value value="1" name="WIREFRAME"/>
+ <value value="2" name="SOLID"/>
+ </bitfield>
+ <bitfield pos="14" name="FILL_MODE_MASK"/>
+ <bitfield high="17" low="16" name="SHADE_MODEL">
+ <value value="0" name="FLAT" brief="Flat shading"/>
+ <value value="1" name="SMOOTH" brief="Gouraud shading"/>
+ </bitfield>
+ <bitfield pos="18" name="SHADE_MODEL_MASK"/>
+ <bitfield pos="22" name="UNK22"/>
+ <bitfield pos="23" name="UNK22_MASK"/>
+ </reg32>
+ <reg32 offset="0x00A38" name="LINE_UNK00A38" value="0x00000000"/>
+ <reg32 offset="0x00A3C" name="LINE_UNK00A3C" value="0x00000000"/>
+ <reg32 offset="0x00A40" name="SHADER_ATTRIBUTES" value="0x00000000" length="10" stride="4">
+ <doc>Flags word per shader attribute</doc>
+ <bitfield high="7" low="0" name="UNK0"/>
+ <bitfield high="15" low="8" name="UNK8"/>
+ </reg32>
+ <reg32 offset="0x00A80" name="VIEWPORT_UNK00A80" value="0x00000000"/>
+ <reg32 offset="0x00A84" name="VIEWPORT_UNK00A84" value="0x00000000"/>
+ </stripe>
+
+ <stripe name="SE" brief="Setup Engine states">
+ <doc>The setup engine takes care of scissor, clipping, and depth scale.</doc>
+ <reg32 offset="0x00C00" name="SCISSOR_LEFT" value="0x00000000" type="fixedp"/>
+ <reg32 offset="0x00C04" name="SCISSOR_TOP" value="0x00000000" type="fixedp"/>
+ <reg32 offset="0x00C08" name="SCISSOR_RIGHT" value="0x45000000" type="fixedp"/>
+ <reg32 offset="0x00C0C" name="SCISSOR_BOTTOM" value="0x45000000" type="fixedp"/>
+ <reg32 offset="0x00C10" name="DEPTH_SCALE" value="0x00000000" type="float"/>
+ <reg32 offset="0x00C14" name="DEPTH_BIAS" value="0x00000000" type="float"/>
+ <reg32 offset="0x00C18" name="CONFIG" value="0x00000000">
+ <bitfield pos="0" name="LAST_PIXEL_ENABLE" brief="Render last pixel of line">
+ <doc>Always disabled for OpenGL</doc>
+ </bitfield>
+ </reg32>
+ <reg32 offset="0x00C1C" name="UNK00C1C" value="0x42000000"/>
+ <reg32 offset="0x00C20" name="CLIP_RIGHT" value="0x00000000" type="fixedp"/>
+ <reg32 offset="0x00C24" name="CLIP_BOTTOM" value="0x00000000" type="fixedp"/>
+ </stripe>
+
+ <stripe name="RA" brief="Raster states">
+ <doc>Configuration for the rasterizer. This mainly controls multisampling.</doc>
+ <reg32 offset="0x00E00" name="CONTROL" value="0x00000001">
+ <bitfield pos="0" name="UNK0"/>
+ <bitfield pos="1" name="UNK1"><doc>Set based on number of PS varyings</doc></bitfield>
+ </reg32>
+ <reg32 offset="0x00E04" name="MULTISAMPLE_UNK00E04" value="0x00000000"/>
+ <reg32 offset="0x00E08" name="DEPTH_UNK00E08" value="0x00000031"/>
+ <reg32 offset="0x00E10" name="MULTISAMPLE_UNK00E10" value="0x00000000" length="4" stride="4"/>
+ <reg32 offset="0x00E40" name="CENTROID_TABLE" value="0x00000000" length="16" stride="4"/>
+ </stripe>
+
+ <stripe name="PS" brief="Pixel Shader states">
+ <doc>The Pixel (Fragment) shader to use is configured here</doc>
+ <reg32 offset="0x01000" name="END_PC" value="0x00000000"/>
+ <reg32 offset="0x01004" name="OUTPUT_REG" value="0x00000000" brief="Register that will contain output color"/>
+ <reg32 offset="0x01008" name="INPUT_COUNT" value="0x00000000">
+ <bitfield high="3" low="0" name="COUNT" type="uint" brief="Number of PS inputs"/>
+ <bitfield high="12" low="8" name="UNK8" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0100C" name="TEMP_REGISTER_CONTROL" brief="Temporary register control" value="0x00000000">
+ <bitfield high="5" low="0" name="NUM_TEMPS" type="uint" brief="Number of temporary registers"/>
+ </reg32>
+ <reg32 offset="0x01010" name="CONTROL" value="0x00000000">
+ <bitfield pos="0" name="BYPASS"/>
+ <bitfield pos="1" name="UNK1"/>
+ </reg32>
+ <reg32 offset="0x01014" name="PERF_COUNTER" brief="Performance counter control"/>
+ <reg32 offset="0x01018" name="START_PC" value="0x01000000"/>
+ <reg32 offset="0x06000" name="INST_MEM" value="0x00000000" length="1024" stride="4"> <!-- instructionCount <= 256 -->
+ <!-- length="instructionCount * 4" -->
+ </reg32>
+ <reg32 offset="0x07000" name="UNIFORMS" value="0x00000000" length="1024" stride="4">
+ <!-- length="fragmentUniforms * 4" -->
+ </reg32>
+ </stripe>
+
+ <stripe name="PE" brief="Pixel Engine states">
+ <doc>The Pixel Engine takes care of writing pixels to the framebuffer, doing
+ blending, depth testing and alpha testing if needed.
+
+ Some flags can be set either per group of bits, or all at once, by using masking flags.
+ Each group of state flags has a masking flag that when set prevents overwriting the flags in that group.
+ These will be called FOO_MASK if the state to be masked is called FOO.
+ </doc>
+ <reg32 offset="0x01400" name="DEPTH_CONFIG" value="0x00000000" masked="yes">
+ <bitfield high="1" low="0" name="DEPTH_MODE">
+ <value value="0" name="NONE"/>
+ <value value="1" name="Z" brief="Z-buffer"/>
+ <value value="2" name="W" brief="W-buffer"/>
+ </bitfield>
+ <bitfield pos="3" name="DEPTH_MODE_MASK"/>
+ <bitfield pos="4" name="DEPTH_FORMAT">
+ <value value="0" name="D16"/>
+ <value value="1" name="D24S8"/>
+ </bitfield>
+ <bitfield pos="5" name="DEPTH_FORMAT_MASK"/>
+ <bitfield high="10" low="8" name="DEPTH_FUNC" type="COMPARE_FUNC" brief="glDepthFunc"/>
+ <bitfield pos="11" name="DEPTH_FUNC_MASK"/>
+ <bitfield pos="12" name="WRITE_ENABLE" brief="glDepthMask"/>
+ <bitfield pos="13" name="WRITE_ENABLE_MASK"/>
+ <bitfield pos="16" name="EARLY_Z"/>
+ <bitfield pos="17" name="EARLY_Z_MASK"/>
+ <bitfield pos="20" name="ONLY_DEPTH"/>
+ <bitfield pos="21" name="ONLY_DEPTH_MASK"/>
+ <bitfield pos="26" name="SUPER_TILED"/>
+ <bitfield pos="27" name="SUPER_TILED_MASK"/>
+ </reg32>
+ <reg32 offset="0x01404" name="DEPTH_NEAR" value="0x00000000" type="float"/>
+ <reg32 offset="0x01408" name="DEPTH_FAR" value="0x00000000" type="float"/>
+ <reg32 offset="0x0140C" name="DEPTH_NORMALIZE" value="0x00000000" type="float"/>
+ <reg32 offset="0x01410" name="DEPTH_ADDR" value="0x00000000" type="VIVM"/> <!-- pixelPipes == 1 -->
+ <reg32 offset="0x01414" name="DEPTH_STRIDE" value="0x00000000"/>
+ <reg32 offset="0x01418" name="STENCIL_OP" value="0x00000000" masked="yes">
+ <bitfield high="2" low="0" name="FUNC_FRONT" type="COMPARE_FUNC" brief="glStencilFunc func (GL_FRONT)"/>
+ <bitfield pos="3" name="FUNC_FRONT_MASK"/>
+ <bitfield high="6" low="4" name="PASS_FRONT" type="STENCIL_OP" brief="glStencilOp dppass (GL_FRONT)"/>
+ <bitfield pos="7" name="PASS_FRONT_MASK"/>
+ <bitfield high="10" low="8" name="FAIL_FRONT" type="STENCIL_OP" brief="glStencilOp sfail (GL_FRONT)"/>
+ <bitfield pos="11" name="FAIL_FRONT_MASK"/>
+ <bitfield high="14" low="12" name="DEPTH_FAIL_FRONT" type="STENCIL_OP" brief="glStencilOp dpfail (GL_FRONT)"/>
+ <bitfield pos="15" name="DEPTH_FAIL_FRONT_MASK"/>
+ <bitfield high="18" low="16" name="FUNC_BACK" type="COMPARE_FUNC" brief="glStencilFunc func (GL_BACK)"/>
+ <bitfield pos="19" name="FUNC_BACK_MASK"/>
+ <bitfield high="22" low="20" name="PASS_BACK" type="STENCIL_OP" brief="glStencilOp dppass (GL_BACK)"/>
+ <bitfield pos="23" name="PASS_BACK_MASK"/>
+ <bitfield high="26" low="24" name="FAIL_BACK" type="STENCIL_OP" brief="glStencilOp sfail (GL_BACK)"/>
+ <bitfield pos="27" name="FAIL_BACK_MASK"/>
+ <bitfield high="30" low="28" name="DEPTH_FAIL_BACK" type="STENCIL_OP" brief="glStencilOp dpfail (GL_BACK)"/>
+ <bitfield pos="31" name="DEPTH_FAIL_BACK_MASK"/>
+ </reg32>
+ <reg32 offset="0x0141C" name="STENCIL_CONFIG" value="0x00000000" masked="yes">
+ <doc>Warning: confusing terminology. WRITE_MASK is the stencil write mask,
+ the state bits can be masked with WRITE_MASK_MASK.</doc>
+ <bitfield high="1" low="0" name="MODE">
+ <value value="0" name="DISABLED" brief="Stencil disabled"/>
+ <value value="1" name="ONE_SIDED" brief="Stencil enabled in one-sided mode"/>
+ <value value="2" name="TWO_SIDED" brief="Stencil enabled in two-sided mode"/>
+ </bitfield>
+ <bitfield pos="4" name="MODE_MASK"/>
+ <bitfield pos="5" name="REF_FRONT_MASK"/>
+ <bitfield pos="6" name="MASK_FRONT_MASK"/>
+ <bitfield pos="7" name="WRITE_MASK_MASK"/>
+ <bitfield high="15" low="8" name="REF_FRONT" brief="glStencilFunc ref (GL_FRONT)">
+ <doc>REF_BACK is in register STENCIL_CONFIG_EXT.</doc>
+ </bitfield>
+ <bitfield high="23" low="16" name="MASK_FRONT" brief="glStencilFunc mask">
+ <doc>XXX there appears to be no specific MASK_BACK, this state is used for both front and back?</doc>
+ </bitfield>
+ <bitfield high="31" low="24" name="WRITE_MASK" brief="glStencilMask"/>
+ </reg32>
+ <reg32 offset="0x01420" name="ALPHA_OP" value="0x00000000" masked="yes">
+ <bitfield pos="0" name="ALPHA_TEST"/>
+ <bitfield pos="1" name="ALPHA_TEST_MASK"/>
+ <bitfield high="6" low="4" name="ALPHA_FUNC" type="COMPARE_FUNC"/>
+ <bitfield pos="7" name="ALPHA_FUNC_MASK"/>
+ <bitfield high="15" low="8" name="ALPHA_REF"/>
+ <bitfield pos="16" name="ALPHA_REF_MASKFUNC_MASK"/>
+ </reg32>
+ <reg32 offset="0x01424" name="ALPHA_BLEND_COLOR" value="0x00000000">
+ <bitfield high="7" low="0" name="B"/>
+ <bitfield high="15" low="8" name="G"/>
+ <bitfield high="23" low="16" name="R"/>
+ <bitfield high="31" low="24" name="A"/>
+ </reg32>
+ <reg32 offset="0x01428" name="ALPHA_CONFIG" value="0x00000000" masked="yes">
+ <bitfield pos="0" name="BLEND_ENABLE_COLOR" brief="Enable alpha blending"/>
+ <bitfield pos="1" name="BLEND_ENABLE_COLOR_MASK"/>
+ <bitfield pos="2" name="SRC_FUNC_COLOR_MASK"/>
+ <bitfield pos="3" name="DST_FUNC_COLOR_MASK"/>
+ <bitfield high="7" low="4" name="SRC_FUNC_COLOR" type="BLEND_FUNC"/>
+ <bitfield high="11" low="8" name="DST_FUNC_COLOR" type="BLEND_FUNC"/>
+ <bitfield high="14" low="12" name="EQ_COLOR" type="BLEND_EQ"/>
+ <bitfield pos="15" name="EQ_COLOR_MASK"/>
+ <bitfield pos="16" name="BLEND_SEPARATE_ALPHA" brief="Enable separate blending for alpha"/>
+ <bitfield pos="17" name="BLEND_SEPARATE_ALPHA_MASK"/>
+ <bitfield pos="18" name="SRC_FUNC_ALPHA_MASK"/>
+ <bitfield pos="19" name="DST_FUNC_ALPHA_MASK"/>
+ <bitfield high="23" low="20" name="SRC_FUNC_ALPHA" type="BLEND_FUNC"/>
+ <bitfield high="27" low="24" name="DST_FUNC_ALPHA" type="BLEND_FUNC"/>
+ <bitfield high="30" low="28" name="EQ_ALPHA" type="BLEND_EQ"/>
+ <bitfield pos="31" name="EQ_ALPHA_MASK"/>
+ </reg32>
+ <reg32 offset="0x0142C" name="COLOR_FORMAT" value="0x00000000" masked="yes">
+ <bitfield high="3" low="0" name="FORMAT" type="RS_FORMAT"/>
+ <bitfield pos="4" name="FORMAT_MASK"/>
+ <bitfield high="11" low="8" name="COMPONENTS" type="RGBA_BITS" brief="glColorMask"/>
+ <bitfield pos="12" name="COMPONENTS_MASK"/>
+ <bitfield pos="16" name="PARTIAL" brief="Set when alpha blending enabled or otherwise the destination is not fully overwritten"/>
+ <bitfield pos="17" name="PARTIAL_MASK"/>
+ <bitfield pos="20" name="SUPER_TILED" brief="64x64 alignment"/>
+ <bitfield pos="21" name="SUPER_TILED_MASK"/>
+ </reg32>
+ <reg32 offset="0x01430" name="COLOR_ADDR" value="0x00000000" type="VIVM"/> <!-- pixelPipes == 1 -->
+ <reg32 offset="0x01434" name="COLOR_STRIDE" value="0x00000000"/>
+ <reg32 offset="0x01454" name="HDEPTH_CONTROL" value="0x00000000">
+ <bitfield high="3" low="0" name="FORMAT">
+ <value value="0" name="DISABLED" brief="Hierarchical Z disabled"/>
+ <value value="5" name="D16" brief="16 bit depth"/>
+ <value value="8" name="D24S8" brief="24 bit depth (+8 bit stencil or padding)"/>
+ </bitfield>
+ </reg32>
+ <reg32 offset="0x01458" name="HDEPTH_ADDR" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x0145C" name="UNK0145C" value="0x00000010"/>
+ <stripe name="UNK01460" length="8" stride="4"> <!-- pixelPipes != 1 -->
+ <!-- length="pixelPipes" -->
+ <reg32 offset="0x1460" name="ADDR_UNK01460" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x1480" name="ADDR_UNK01480" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x1500" name="ADDR_UNK01500" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x1520" name="ADDR_UNK01520" value="0x00000000" type="VIVM"/>
+ </stripe>
+ <reg32 offset="0x014A0" name="STENCIL_CONFIG_EXT" value="0x00000000" masked="yes">
+ <bitfield high="7" low="0" name="REF_BACK" brief="glStencilFunc ref (GL_BACK)"/>
+ <bitfield pos="8" name="REF_BACK_MASK"/>
+ <bitfield pos="9" name="UNK16_MASK"/>
+ <bitfield high="31" low="16" name="UNK16"/>
+ </reg32>
+ <reg32 offset="0x014A4" name="LOGIC_OP" masked="yes" value="0x000E400C">
+ <!-- only supported if feature bit LOGIC_OP present.
+ Either a coincidence or due to shared roots in DirectX: same enum as Gallium3D PIPE_LOGICOP -->
+ <bitfield high="3" low="0" name="OP" type="LOGIC_OP"/>
+ <bitfield pos="4" name="OP_MASK"/>
+ </reg32>
+ <reg32 offset="0x014A8" name="DITHER" value="0xFFFFFFFF" length="2"/>
+ <reg32 offset="0x014B0" name="UNK014B0" value="0x00000000"/>
+ <reg32 offset="0x014B4" name="UNK014B4" value="0x00000000"/>
+ <reg32 offset="0x01580" name="UNK01580" value="0x00000000" length="3" stride="4"/>
+ </stripe>
+
+ <stripe name="CO" brief="Compose states">
+ <doc>Hardware composer. This functionality is present on some GCxxxx chips and allows
+ for blending surfaces together with Porter-Diff composition methods, to accelerate the
+ likes of Surfaceflinger (Android).</doc>
+ <reg32 offset="0x03008" name="UNK03008" value="0x00000000"/>
+ <reg32 offset="0x0300C" name="KICKER"/>
+ <reg32 offset="0x03010" name="UNK03010"/>
+ <reg32 offset="0x03014" name="UNK03014"/>
+ <reg32 offset="0x03018" name="UNK03018"/>
+ <reg32 offset="0x0301C" name="UNK0301C"/>
+ <reg32 offset="0x03020" name="UNK03020"/>
+ <reg32 offset="0x03024" name="UNK03024"/>
+ <reg32 offset="0x03040" name="UNK03040"/>
+ <reg32 offset="0x03044" name="UNK03044"/>
+ <reg32 offset="0x03048" name="UNK03048"/>
+ <stripe name="SAMPLER" length="8" stride="4">
+ <reg32 offset="0x03060" name="UNK03060"/>
+ <reg32 offset="0x03080" name="UNK03080"/>
+ <reg32 offset="0x030A0" name="UNK030A0"/>
+ <reg32 offset="0x030C0" name="UNK030C0"/>
+ <reg32 offset="0x030E0" name="UNK030E0"/>
+ <reg32 offset="0x03100" name="UNK03100"/>
+ <reg32 offset="0x03120" name="UNK03120"/>
+ <reg32 offset="0x03140" name="UNK03140"/>
+ <reg32 offset="0x03160" name="UNK03160"/>
+ <reg32 offset="0x03180" name="UNK03180"/>
+ <reg32 offset="0x031A0" name="UNK031A0"/>
+ <reg32 offset="0x031C0" name="UNK031C0"/>
+ <reg32 offset="0x031E0" name="UNK031E0"/>
+ </stripe>
+ <array offset="0x03200" name="ADDR_UNK03200" length="8" stride="0x20">
+ <reg32 offset="0" name="PPIPE" length="8"/> <!-- sampler*0x20 + pixelpipe*0x4 -->
+ </array>
+ </stripe>
+
+ <stripe name="RS" brief="Resolve states">
+ <doc>To my current understanding, RESOLVE is a multifunctional copy/fill engine that can copy blocks of pixels from
+ one place in memory to another, actually clearing tiles that are marked as cleared in the process.
+ Other capabilities are:
+
+ - Conversion between pixel formats
+ - Downsampling (2x horizontal or horizontal and vertical)
+ - Fill with constant value
+ - Partial fill (only clear part of the channels)
+ - Tiling / untiling, for normal tiled and supertiled surfaces
+ - Swap blue and red channels, flip image in Y
+ - Endian swapping
+ - Fill tiles that are marked as 'cleared' in the Tile Status
+
+ The following render target tilings are possible:
+
+ A B
+ 0 0 Linear
+ 1 0 Tiled (4x4, like textures)
+ 0 1 (same as tiled=0, supertiled=0)
+ 1 1 Supertiled (64x64)
+
+ A) tiled: SOURCE_TILED, DEST_TILED in CONFIG word
+ B) supertiled: TILING bit in SOURCE_STRIDE / DEST_STRIDE
+ </doc>
+ <reg32 offset="0x01600" name="KICKER" brief="Resolve start" value="0x00000000">
+ <doc>Write some value to this register to kick off resolver</doc>
+ </reg32>
+ <reg32 offset="0x01604" name="CONFIG" brief="Resolve configuration register" value="0x00000000">
+ <bitfield high="4" low="0" name="SOURCE_FORMAT" type="RS_FORMAT" brief="Source color format"/>
+ <bitfield pos="5" name="DOWNSAMPLE_X" brief="Downsampling horizontally"/>
+ <bitfield pos="6" name="DOWNSAMPLE_Y" brief="Downsampling vertically"/>
+ <bitfield pos="7" name="SOURCE_TILED" brief="Source is tiled"/>
+ <bitfield high="12" low="8" name="DEST_FORMAT" type="RS_FORMAT" brief="Destination color format"/>
+ <bitfield pos="14" name="DEST_TILED" brief="Destination is tiled"/>
+ <bitfield pos="29" name="SWAP_RB" brief="Swap red and blue"/>
+ <bitfield pos="30" name="FLIP" brief="Flip image in Y direction"/>
+ </reg32>
+ <reg32 offset="0x01608" name="SOURCE_ADDR" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x0160C" name="SOURCE_STRIDE" value="0x00000000">
+ <bitfield high="17" low="0" name="STRIDE" brief="Source stride"/>
+ <bitfield pos="31" name="TILING" brief="Source is tiled"/>
+ </reg32>
+ <reg32 offset="0x01610" name="DEST_ADDR" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x01614" name="DEST_STRIDE" value="0x00000000">
+ <bitfield high="17" low="0" name="STRIDE" brief="Destination stride"/>
+ <bitfield pos="31" name="TILING" brief="Destination is tiled"/>
+ </reg32>
+ <reg32 offset="0x01620" name="WINDOW_SIZE" value="0x00000000" brief="Size of area to resolve">
+ <doc>
+ When downsampling the source and destination size will be different.
+ In this case, the WINDOW_SIZE will be the (unscaled) source size.
+ </doc>
+ <bitfield high="31" low="16" name="HEIGHT" type="uint"/>
+ <bitfield high="15" low="0" name="WIDTH" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01630" name="DITHER" value="0x00000000" length="2" stride="4"/>
+ <reg32 offset="0x0163C" name="CLEAR_CONTROL" value="0x00000000">
+ <bitfield high="15" low="0" name="BITS" brief="Affects which channels of which tiles are cleared">
+ <doc>
+ Four groups (per tile) of four bits (per channel) that affect which channels of which tiles are cleared.
+ In mode 'enabled' only the lower four bits are used, in 'enabled2' all four groups are used.
+
+ Components that are disabled are not written at all by the clear logic (they keep their old value)
+ they are not copied from the source.
+ </doc>
+ </bitfield>
+ <bitfield high="17" low="16" name="MODE" brief="Enable clearing">
+ <doc>
+ Depending on the clear mode, the RS does different things:
+ - If disabled, it is a copy engine
+ - If enabled, it fills the target area with FILL_VALUE(0) and disregards the source
+ - If enabled2, it fills the target area with the four FILL_VALUEs (results in vertical stripes of width 4,
+ at least with supertiled target) and disregards the source.
+ </doc>
+ <value value="0" name="DISABLED"/>
+ <value value="1" name="ENABLED1" brief="Clear single value"/>
+ <value value="2" name="ENABLED4" brief="Clear with four alternating tile values"/>
+ <value value="3" name="ENABLED4_2" brief="Clear with alternating tile values (2)"/>
+ </bitfield>
+ </reg32>
+ <reg32 offset="0x01640" name="FILL_VALUE" value="0x00000000" length="4" stride="4"/>
+ <reg32 offset="0x01650" name="FLUSH_CACHE" brief="Flush resolve cache" value="0x00000000">
+ <bitfield pos="0" name="FLUSH"/>
+ </reg32>
+ <reg32 offset="0x016A0" name="EXTRA_CONFIG" value="0x00000000">
+ <bitfield high="1" low="0" name="AA" brief="Anti-aliasing mode (not used for MSAA)"/>
+ <bitfield high="9" low="8" name="ENDIAN" type="ENDIAN_MODE"/>
+ </reg32>
+ <reg32 offset="0x016B4" name="UNK016B4" value="0x00000000"/>
+ <stripe name="UNK016C0" length="8" stride="4"> <!-- pixelPipes > 1 -->
+ <!-- length="pixelPipes" -->
+ <reg32 offset="0x016C0" name="UNK016C0" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x016E0" name="UNK016E0" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x01700" name="UNK01700" value="0x00000000"/>
+ </stripe>
+ </stripe>
+
+ <stripe name="TS" brief="Tile Status">
+ <doc>
+ Tile status block contains information about the tiles to be resolved.
+ It is used by the PE (to read/update tile status) as well as the RS (to read tile status).
+ </doc>
+ <reg32 offset="0x01654" name="MEM_CONFIG" brief="Memory configuration" value="0x00200000">
+ <doc>
+ Tile status config. Setting this value to 0 disables tile status and makes the resolve
+ work like a normal copy engine.
+ </doc>
+ <bitfield pos="0" name="DEPTH_FAST_CLEAR" brief="Clear depth tiles on resolve"/>
+ <bitfield pos="1" name="COLOR_FAST_CLEAR" brief="Clear color tiles on resolve"/>
+ <bitfield pos="3" name="DEPTH_16BPP"/>
+ <bitfield pos="4" name="DEPTH_AUTO_DISABLE" brief="Auto disable fast clear for depth"/>
+ <bitfield pos="5" name="COLOR_AUTO_DISABLE" brief="Auto disable fast clear for color"/>
+ <bitfield pos="6" name="DEPTH_COMPRESSION" brief="Enable depth compression"/>
+ <bitfield pos="7" name="MSAA" brief="This bit is enabled when MSAA samples >= 2">
+ <doc>
+ The main bits for switching MSAA in rendering are in register #0x03818, these bits
+ in the TS memory configuration appear to affect the writing of tiles in a minor way.
+ </doc>
+ </bitfield>
+ <bitfield high="11" low="8" name="MSAA_FORMAT">
+ <value value="0" name="A4R4G4B4"/>
+ <value value="1" name="A1R5G5B5"/>
+ <value value="2" name="R5G6B5"/>
+ <value value="3" name="A8R8G8B8"/>
+ <value value="4" name="X8R8G8B8"/>
+ </bitfield>
+ </reg32>
+ <reg32 offset="0x01658" name="COLOR_STATUS_BASE" brief="Color tile status base address" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x0165C" name="COLOR_SURFACE_BASE" brief="Color surface base address" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x01660" name="COLOR_CLEAR_VALUE" brief="Color clear value" value="0x00000000"/>
+ <reg32 offset="0x01664" name="DEPTH_STATUS_BASE" brief="Depth tile status base address" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x01668" name="DEPTH_SURFACE_BASE" brief="Depth surface base address" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x0166C" name="DEPTH_CLEAR_VALUE" brief="Depth clear value" value="0x00000000"/>
+ <reg32 offset="0x01670" name="COLOR_AUTO_DISABLE_COUNT" brief="Auto disable depth counter" value="0x00000000"/>
+ <reg32 offset="0x01674" name="DEPTH_AUTO_DISABLE_COUNT" brief="Auto disable color counter" value="0x00000000"/>
+ <reg32 offset="0x016A4" name="HDEPTH_BASE" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x016A8" name="HDEPTH_CLEAR_VALUE" brief="Hierarchical depth clear value" value="0x00000000"/>
+ <stripe name="SAMPLER" length="8" stride="4"> <!-- Tile status for samplers -->
+ <reg32 offset="0x01720" name="CONFIG" value="0x00000000">
+ <bitfield high="1" low="0" name="ENABLE"/>
+ <bitfield high="7" low="4" name="FORMAT"/>
+ </reg32>
+ <reg32 offset="0x01740" name="STATUS_BASE" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x01760" name="CLEAR_VALUE" value="0x00000000"/>
+ </stripe>
+ </stripe>
+
+ <stripe name="YUV" brief="YUV tiler states">
+ <doc>The YUV tiler can combine planar YUV formats to RGB or non-planar YUV formats.</doc>
+ <reg32 offset="0x01678" name="UNK01678" value="0x00000000"/>
+ <reg32 offset="0x0167C" name="UNK0167C" value="0x00000000"/>
+ <reg32 offset="0x01680" name="UNK01680" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x01684" name="UNK01684" value="0x00000000"/>
+ <reg32 offset="0x01688" name="UNK01688" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x0168C" name="UNK0168C" value="0x00000000"/>
+ <reg32 offset="0x01690" name="UNK01690" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x01694" name="UNK01694" value="0x00000000"/>
+ <reg32 offset="0x01698" name="UNK01698" value="0x00000000" type="VIVM"/>
+ <reg32 offset="0x0169C" name="UNK0169C" value="0x00000000"/>
+ </stripe>
+
+ <!-- register descriptions shared between TE.SAMPLER and NTE.SAMPLER -->
+ <bitset name="TE_SAMPLER_CONFIG0" inline="yes">
+ <bitfield high="2" low="0" name="TYPE" type="TEXTURE_TYPE"/>
+ <bitfield high="4" low="3" name="UWRAP" type="TEXTURE_WRAPMODE"/>
+ <bitfield high="6" low="5" name="VWRAP" type="TEXTURE_WRAPMODE"/>
+ <bitfield high="8" low="7" name="MIN" type="TEXTURE_FILTER"/>
+ <bitfield high="10" low="9" name="MIP" type="TEXTURE_FILTER"/>
+ <bitfield high="12" low="11" name="MAG" type="TEXTURE_FILTER"/>
+ <bitfield high="17" low="13" name="FORMAT" type="TEXTURE_FORMAT"/>
+ </bitset>
+ <bitset name="TE_SAMPLER_SIZE" inline="yes">
+ <bitfield high="15" low="0" name="WIDTH" type="uint"/>
+ <bitfield high="31" low="16" name="HEIGHT" type="uint"/>
+ </bitset>
+ <bitset name="TE_SAMPLER_LOG_SIZE" inline="yes">
+ <bitfield high="9" low="0" name="WIDTH" type="fixedp"/>
+ <bitfield high="19" low="10" name="HEIGHT" type="fixedp"/>
+ </bitset>
+ <bitset name="TE_SAMPLER_LOD_CONFIG" inline="yes">
+ <bitfield pos="0" name="BIAS_ENABLE" brief="Enable LOD bias"/>
+ <bitfield high="10" low="1" name="MAX" type="fixedp" brief="Maximum LOD level">
+ <doc>
+ This fixed-point value is the maximum LOD level. It can be a fractional value, up to the number of defined mipmaps.
+ </doc>
+ </bitfield>
+ <bitfield high="20" low="11" name="MIN" type="fixedp" brief="Minimum LOD level">
+ <doc>
+ This fixed-point value is the minimum LOD level. It can be a fractional value.
+ </doc>
+ </bitfield>
+ <bitfield high="30" low="21" name="BIAS" type="fixedp" brief="LOD bias">
+ <doc>
+ This fixed-point value is added to the computed LOD level when BIAS_ENABLE is on.
+ It appears that it can also be negative by using two's complement arithmetic.
+ </doc>
+ </bitfield>
+ </bitset>
+ <bitset name="TE_SAMPLER_CONFIG1" inline="yes">
+ <bitfield high="4" low="0" name="FORMAT_EXT" type="TEXTURE_FORMAT_EXT"/>
+ <bitfield high="10" low="8" name="SWIZZLE_R" type="TEXTURE_SWIZZLE"/>
+ <bitfield high="14" low="12" name="SWIZZLE_G" type="TEXTURE_SWIZZLE"/>
+ <bitfield high="18" low="16" name="SWIZZLE_B" type="TEXTURE_SWIZZLE"/>
+ <bitfield high="22" low="20" name="SWIZZLE_A" type="TEXTURE_SWIZZLE"/>
+ </bitset>
+ <stripe name="TE" brief="TExture sampler states">
+ <doc>Texture sampling, filtering, LOD, etc</doc>
+ <stripe name="SAMPLER" length="12" stride="4">
+ <reg32 offset="0x2000" name="CONFIG0" value="0x00000000" type="TE_SAMPLER_CONFIG0"/>
+ <reg32 offset="0x2040" name="SIZE" value="0x00000000" type="TE_SAMPLER_SIZE"/>
+ <reg32 offset="0x2080" name="LOG_SIZE" value="0x00000000" type="TE_SAMPLER_LOG_SIZE"/>
+ <reg32 offset="0x20C0" name="LOD_CONFIG" value="0x00000000" type="TE_SAMPLER_LOD_CONFIG"/>
+ <reg32 offset="0x2100" name="UNK02100" value="0x00000000"/>
+ <reg32 offset="0x2140" name="UNK02140" value="0x00000000"/>
+ <reg32 offset="0x2180" name="UNK02180" value="0x00000000"/>
+ <reg32 offset="0x21C0" name="CONFIG1" value="0x00321000" type="TE_SAMPLER_CONFIG1"/>
+ <reg32 offset="0x2200" name="UNK02200" value="0x00000000"/>
+ <reg32 offset="0x2240" name="UNK02240" value="0x00000000"/>
+ <reg32 offset="0x2400" name="LOD_ADDR" length="14" stride="0x40" type="VIVM"/> <!-- Base address, per LOD level -->
+ </stripe>
+ </stripe>
+
+ <stripe name="NTE" brief="New texture states">
+ <doc>Extra texture states for newer hardware. These exist if chipMinorFeatures2 bit 11 set.</doc>
+ <array offset="0x10000" name="SAMPLER" length="32" stride="4">
+ <reg32 offset="0x000" name="CONFIG0" value="0x00000000" type="TE_SAMPLER_CONFIG0"/>
+ <reg32 offset="0x080" name="SIZE" value="0x00000000" type="TE_SAMPLER_SIZE"/>
+ <reg32 offset="0x100" name="LOG_SIZE" value="0x00000000" type="TE_SAMPLER_LOG_SIZE"/>
+ <reg32 offset="0x180" name="LOD_CONFIG" value="0x00000000" type="TE_SAMPLER_LOD_CONFIG"/>
+ <reg32 offset="0x200" name="UNK10200" value="0x00000000"/>
+ <reg32 offset="0x280" name="UNK10280" value="0x00000000"/>
+ <reg32 offset="0x300" name="UNK10300" value="0x00000000"/>
+ <reg32 offset="0x380" name="CONFIG1" value="0x00321000" type="TE_SAMPLER_CONFIG1"/>
+ <reg32 offset="0x400" name="UNK10400" value="0x00000000"/>
+ <reg32 offset="0x480" name="UNK10480" value="0x00000000"/>
+ </array>
+ <array offset="0x10800" name="SAMPLER_ADDR" length="32" stride="64"> <!-- Per sampler -->
+ <!-- length="texBlockCount"
+ where texBlockCount=12 if chipModel == GC2000 && chipRevision == 0x5108, otherwise 32
+ -->
+ <reg32 offset="0" name="LOD" length="14" stride="4" type="VIVM"/> <!-- Base address, per LOD level -->
+ </array>
+ <reg32 offset="0x12000" name="UNK12000" value="0x00000000" length="256" stride="4"/> <!-- chipMinorFeatures2 bit 15 set -->
+ <reg32 offset="0x12400" name="UNK12400" value="0x00000000" length="256" stride="4"/> <!-- chipMinorFeatures2 bit 15 set -->
+ </stripe>
+
+ <stripe name="SH" brief="Unified shader instruction memory">
+ <doc>Shader instruction memory on new hardware that supports more than 256, or more than
+ 1024 shader instructions (different areas are used based on these cases).</doc>
+ <reg32 offset="0x0085C" name="UNK0085C" value="0x00000000"/> <!-- instructionCount > 1024 -->
+ <reg32 offset="0x00860" name="UNK00860" value="0x00000000"/> <!-- instructionCount > 1024 -->
+ <reg32 offset="0x0101C" name="UNK0101C" value="0x00000100"/> <!-- instructionCount > 1024 -->
+ <reg32 offset="0x20000" name="UNK20000" value="0x00000000" length="8192" stride="4"> <!-- instructionCount > 1024 -->
+ <!-- length="instructionCount * 4" -->
+ </reg32>
+ <reg32 offset="0x0C000" name="UNK0C000" value="0x00000000" length="4096" stride="4"> <!-- 256 > instructionCount > 1024 -->
+ <!-- length="instructionCount * 4" -->
+ </reg32>
+ <reg32 offset="0x08000" name="UNK0C000_MIRROR" value="0x00000000" length="4096" stride="4"> <!-- 256 > instructionCount > 1024 -->
+ <!-- length="instructionCount * 4" -->
+ </reg32>
+ </stripe>
+</domain>
+</database>
+
generated by cgit (git 2.34.1) at 2025-07-16 16:41:16 +0000