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-rw-r--r--src/driver/etna_pipe.c45
-rw-r--r--src/driver/etna_pipe.h2
-rw-r--r--src/driver/etna_resource.c14
-rw-r--r--src/driver/etna_screen.c5
-rw-r--r--src/driver/etna_surface.c2
-rw-r--r--src/etnaviv/etna_bo.c64
-rw-r--r--src/etnaviv/etna_rs.c82
-rw-r--r--src/etnaviv/etna_rs.h4
-rw-r--r--src/lib/fbdemos.c3
9 files changed, 178 insertions, 43 deletions
diff --git a/src/driver/etna_pipe.c b/src/driver/etna_pipe.c
index 372b835..216b86f 100644
--- a/src/driver/etna_pipe.c
+++ b/src/driver/etna_pipe.c
@@ -195,7 +195,10 @@ static void reset_context(struct pipe_context *restrict pipe)
/*01404*/ EMIT_STATE(PE_DEPTH_NEAR, PE_DEPTH_NEAR);
/*01408*/ EMIT_STATE(PE_DEPTH_FAR, PE_DEPTH_FAR);
/*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, PE_DEPTH_NORMALIZE);
- /*01410*/ EMIT_STATE(PE_DEPTH_ADDR, PE_DEPTH_ADDR);
+ if (ctx->conn->chip.pixel_pipes == 1)
+ {
+ /*01410*/ EMIT_STATE(PE_DEPTH_ADDR, PE_DEPTH_ADDR);
+ }
/*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, PE_DEPTH_STRIDE);
/*01418*/ EMIT_STATE(PE_STENCIL_OP, PE_STENCIL_OP);
/*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, PE_STENCIL_CONFIG);
@@ -203,16 +206,22 @@ static void reset_context(struct pipe_context *restrict pipe)
/*01424*/ EMIT_STATE(PE_ALPHA_BLEND_COLOR, PE_ALPHA_BLEND_COLOR);
/*01428*/ EMIT_STATE(PE_ALPHA_CONFIG, PE_ALPHA_CONFIG);
/*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, PE_COLOR_FORMAT);
- /*01430*/ EMIT_STATE(PE_COLOR_ADDR, PE_COLOR_ADDR);
- /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, PE_COLOR_STRIDE);
- /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, PE_HDEPTH_CONTROL);
- for(int x=0; x<8; ++x)
+ if (ctx->conn->chip.pixel_pipes == 1)
{
- /*01460*/ EMIT_STATE(PE_PIPE_COLOR_ADDR(x), PE_PIPE_COLOR_ADDR[x]);
+ /*01430*/ EMIT_STATE(PE_COLOR_ADDR, PE_COLOR_ADDR);
}
- for(int x=0; x<8; ++x)
+ /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, PE_COLOR_STRIDE);
+ /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, PE_HDEPTH_CONTROL);
+ if (ctx->conn->chip.pixel_pipes != 1)
{
- /*01480*/ EMIT_STATE(PE_PIPE_DEPTH_ADDR(x), PE_PIPE_DEPTH_ADDR[x]);
+ for(int x=0; x<ctx->conn->chip.pixel_pipes; ++x)
+ {
+ /*01460*/ EMIT_STATE(PE_PIPE_COLOR_ADDR(x), PE_PIPE_COLOR_ADDR[x]);
+ }
+ for(int x=0; x<ctx->conn->chip.pixel_pipes; ++x)
+ {
+ /*01480*/ EMIT_STATE(PE_PIPE_DEPTH_ADDR(x), PE_PIPE_DEPTH_ADDR[x]);
+ }
}
/*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, PE_STENCIL_CONFIG_EXT);
/*014A4*/ EMIT_STATE(PE_LOGIC_OP, PE_LOGIC_OP);
@@ -969,15 +978,15 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe,
cbuf->surf.offset, cbuf->surf.stride*4);
}
- struct etna_bo *bo = etna_resource(cbuf->base.texture)->bo;
+ struct etna_resource *res = etna_resource(cbuf->base.texture);
if (priv->ctx->conn->chip.pixel_pipes == 1)
{
- cs->PE_COLOR_ADDR = etna_bo_gpu_address(bo) + cbuf->surf.offset;
+ cs->PE_COLOR_ADDR = res->pipe_addr[0];
}
else if (priv->ctx->conn->chip.pixel_pipes == 2)
{
- cs->PE_PIPE_COLOR_ADDR[0] = etna_bo_gpu_address(bo) + cbuf->surf.offset;
- cs->PE_PIPE_COLOR_ADDR[1] = etna_bo_gpu_address(bo) + cbuf->surf.offset; /* TODO */
+ cs->PE_PIPE_COLOR_ADDR[0] = res->pipe_addr[0];
+ cs->PE_PIPE_COLOR_ADDR[1] = res->pipe_addr[1];
}
cs->PE_COLOR_STRIDE = cbuf->surf.stride;
if(cbuf->surf.ts_size)
@@ -986,7 +995,7 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe,
ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
cs->TS_COLOR_STATUS_BASE = etna_bo_gpu_address(ts_bo) + cbuf->surf.ts_offset;
- cs->TS_COLOR_SURFACE_BASE = etna_bo_gpu_address(bo) + cbuf->surf.offset;
+ cs->TS_COLOR_SURFACE_BASE = res->pipe_addr[0];
}
/* MSAA */
if(cbuf->base.texture->nr_samples > 1)
@@ -1011,15 +1020,15 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe,
VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z;
/* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
/* merged with depth_stencil_alpha */
- struct etna_bo *bo = etna_resource(zsbuf->base.texture)->bo;
+ struct etna_resource *res = etna_resource(zsbuf->base.texture);
if (priv->ctx->conn->chip.pixel_pipes == 1)
{
- cs->PE_DEPTH_ADDR = etna_bo_gpu_address(bo) + zsbuf->surf.offset;
+ cs->PE_DEPTH_ADDR = res->pipe_addr[0];
}
else if (priv->ctx->conn->chip.pixel_pipes == 2)
{
- cs->PE_PIPE_DEPTH_ADDR[0] = etna_bo_gpu_address(bo) + zsbuf->surf.offset;
- cs->PE_PIPE_DEPTH_ADDR[1] = etna_bo_gpu_address(bo) + zsbuf->surf.offset; /* TODO */
+ cs->PE_PIPE_DEPTH_ADDR[0] = res->pipe_addr[0];
+ cs->PE_PIPE_DEPTH_ADDR[1] = res->pipe_addr[1];
}
cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
@@ -1030,7 +1039,7 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe,
ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
cs->TS_DEPTH_STATUS_BASE = etna_bo_gpu_address(ts_bo) + zsbuf->surf.ts_offset;
- cs->TS_DEPTH_SURFACE_BASE = etna_bo_gpu_address(bo) + zsbuf->surf.offset;
+ cs->TS_DEPTH_SURFACE_BASE = res->pipe_addr[0];
}
ts_mem_config |= (depth_bits == 16 ? VIVS_TS_MEM_CONFIG_DEPTH_16BPP : 0);
/* MSAA */
diff --git a/src/driver/etna_pipe.h b/src/driver/etna_pipe.h
index 54a113a..c9d59b1 100644
--- a/src/driver/etna_pipe.h
+++ b/src/driver/etna_pipe.h
@@ -87,6 +87,8 @@ struct etna_resource
struct etna_resource_level levels[ETNA_NUM_LOD];
struct etna_pipe_context *last_ctx; /* Last bound context */
+
+ uint32_t pipe_addr[2];
};
struct etna_surface
diff --git a/src/driver/etna_resource.c b/src/driver/etna_resource.c
index 4782804..4389a2f 100644
--- a/src/driver/etna_resource.c
+++ b/src/driver/etna_resource.c
@@ -146,7 +146,15 @@ static struct pipe_resource * etna_screen_resource_create(struct pipe_screen *sc
else
layout = ETNA_LAYOUT_TILED;
}
- /* XXX multi tiled formats */
+
+ /* multi tiled formats */
+ if (priv->dev->chip.pixel_pipes > 1)
+ {
+ if (layout == ETNA_LAYOUT_TILED)
+ layout = ETNA_LAYOUT_MULTI_TILED;
+ if (layout == ETNA_LAYOUT_SUPER_TILED)
+ layout = ETNA_LAYOUT_MULTI_SUPERTILED;
+ }
/* Determine scaling for antialiasing, allow override using debug flag */
int nr_samples = templat->nr_samples;
@@ -237,6 +245,10 @@ static struct pipe_resource * etna_screen_resource_create(struct pipe_screen *sc
resource->ts_bo = 0; /* TS is only created when first bound to surface */
pipe_reference_init(&resource->base.reference, 1);
+ /* calculate pipe addresses */
+ resource->pipe_addr[0] = etna_bo_gpu_address(resource->bo) + resource->levels[0].offset;
+ resource->pipe_addr[1] = etna_bo_gpu_address(resource->bo) + resource->levels[0].offset + (resource->levels[0].size / 2);
+
if(DBG_ENABLED(ETNA_DBG_ZERO))
{
void *map = etna_bo_map(bo);
diff --git a/src/driver/etna_screen.c b/src/driver/etna_screen.c
index f381c7d..e86025e 100644
--- a/src/driver/etna_screen.c
+++ b/src/driver/etna_screen.c
@@ -474,11 +474,12 @@ static void etna_screen_flush_frontbuffer( struct pipe_screen *screen,
etna_compile_rs_state(ctx, &copy_to_screen, &(struct rs_state){
.source_format = translate_rt_format(rt_resource->base.format, false),
.source_tiling = rt_resource->layout,
- .source_addr = etna_bo_gpu_address(rt_resource->bo) + rt_resource->levels[level].offset,
+ .source_addr[0] = rt_resource->pipe_addr[0],
+ .source_addr[1] = rt_resource->pipe_addr[1],
.source_stride = rt_resource->levels[level].stride,
.dest_format = drawable->rs_format,
.dest_tiling = ETNA_LAYOUT_LINEAR,
- .dest_addr = etna_bo_gpu_address(drawable->bo),
+ .dest_addr[0] = etna_bo_gpu_address(drawable->bo),
.dest_stride = drawable->stride,
.downsample_x = msaa_xscale > 1,
.downsample_y = msaa_yscale > 1,
diff --git a/src/driver/etna_surface.c b/src/driver/etna_surface.c
index 2442758..81ff249 100644
--- a/src/driver/etna_surface.c
+++ b/src/driver/etna_surface.c
@@ -92,7 +92,7 @@ static struct pipe_surface *etna_pipe_create_surface(struct pipe_context *pipe,
etna_compile_rs_state(priv->ctx, &surf->clear_command, &(struct rs_state){
.source_format = RS_FORMAT_A8R8G8B8,
.dest_format = RS_FORMAT_A8R8G8B8,
- .dest_addr = etna_bo_gpu_address(ts_bo) + surf->surf.ts_offset,
+ .dest_addr[0] = etna_bo_gpu_address(ts_bo) + surf->surf.ts_offset,
.dest_stride = 0x40,
.dest_tiling = ETNA_LAYOUT_TILED,
.dither = {0xffffffff, 0xffffffff},
diff --git a/src/etnaviv/etna_bo.c b/src/etnaviv/etna_bo.c
index 8c6069e..655e856 100644
--- a/src/etnaviv/etna_bo.c
+++ b/src/etnaviv/etna_bo.c
@@ -55,6 +55,68 @@ struct etna_bo {
viv_usermem_t usermem_info;
};
+#ifdef DEBUG
+static const char *etna_bo_surf_type(struct etna_bo *mem)
+{
+ const char *ret = NULL;
+
+ switch (mem->type) {
+ case VIV_SURF_UNKNOWN:
+ ret = "VIV_SURF_UNKNOWN";
+ break;
+
+ case VIV_SURF_INDEX:
+ ret = "VIV_SURF_INDEX";
+ break;
+
+ case VIV_SURF_VERTEX:
+ ret = "VIV_SURF_VERTEX";
+ break;
+
+ case VIV_SURF_TEXTURE:
+ ret = "VIV_SURF_TEXTURE";
+ break;
+
+ case VIV_SURF_RENDER_TARGET:
+ ret = "VIV_SURF_RENDER_TARGET";
+ break;
+
+ case VIV_SURF_DEPTH:
+ ret = "VIV_SURF_DEPTH";
+ break;
+
+ case VIV_SURF_BITMAP:
+ ret = "VIV_SURF_BITMAP";
+ break;
+
+ case VIV_SURF_TILE_STATUS:
+ ret = "VIV_SURF_TILE_STATUS";
+ break;
+
+ case VIV_SURF_IMAGE:
+ ret = "VIV_SURF_IMAGE";
+ break;
+
+ case VIV_SURF_MASK:
+ ret = "VIV_SURF_MASK";
+ break;
+
+ case VIV_SURF_SCISSOR:
+ ret = "VIV_SURF_SCISSOR";
+ break;
+
+ case VIV_SURF_HIERARCHICAL_DEPTH:
+ ret = "VIV_SURF_HIERARCHICAL_DEPTH";
+ break;
+
+ default:
+ ret = "hmmmm?";
+ break;
+ }
+ return ret;
+}
+#endif
+
/* Lock (map) memory into both CPU and GPU memory space. */
static int etna_bo_lock(struct viv_conn *conn, struct etna_bo *mem)
{
@@ -157,7 +219,7 @@ struct etna_bo* etna_bo_new(struct viv_conn *conn, size_t bytes, uint32_t flags)
return NULL;
}
#ifdef DEBUG
- printf("Allocated: mem=%p node=%08x size=%08x\n", mem, (uint32_t)mem->node, mem->size);
+ printf("Allocated: type:%s mem=%p node=%08x size=%08x\n", etna_bo_surf_type(mem), mem, (uint32_t)mem->node, mem->size);
#endif
int status = etna_bo_lock(conn, mem);
if(status != ETNA_OK)
diff --git a/src/etnaviv/etna_rs.c b/src/etnaviv/etna_rs.c
index a03662a..45321a5 100644
--- a/src/etnaviv/etna_rs.c
+++ b/src/etnaviv/etna_rs.c
@@ -26,6 +26,11 @@
#include <etnaviv/state.xml.h>
#include <etnaviv/state_3d.xml.h>
+//#define DEBUG
+#ifdef DEBUG
+# include <stdio.h>
+#endif
+
/* Some kind of RS flush, used in the older drivers */
void etna_warm_up_rs(struct etna_ctx *cmdbuf, viv_addr_t aux_rt_physical, viv_addr_t aux_rt_ts_physical)
{
@@ -57,6 +62,11 @@ void etna_compile_rs_state(struct etna_ctx *restrict ctx, struct compiled_rs_sta
/* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */
unsigned source_stride_shift = (rs->source_tiling != ETNA_LAYOUT_LINEAR) ? 2 : 0;
unsigned dest_stride_shift = (rs->dest_tiling != ETNA_LAYOUT_LINEAR) ? 2 : 0;
+
+ /* tiling == ETNA_LAYOUT_MULTI_TILED or ETNA_LAYOUT_MULTI_SUPERTILED? */
+ bool source_multi = (rs->source_tiling & 0x4)?true:false;
+ bool dest_multi = (rs->dest_tiling & 0x4)?true:false;
+
/* TODO could just pre-generate command buffer, would simply submit to one memcpy */
SET_STATE(RS_CONFIG, VIVS_RS_CONFIG_SOURCE_FORMAT(rs->source_format) |
(rs->downsample_x?VIVS_RS_CONFIG_DOWNSAMPLE_X:0) |
@@ -66,20 +76,30 @@ void etna_compile_rs_state(struct etna_ctx *restrict ctx, struct compiled_rs_sta
((rs->dest_tiling&1)?VIVS_RS_CONFIG_DEST_TILED:0) |
((rs->swap_rb)?VIVS_RS_CONFIG_SWAP_RB:0) |
((rs->flip)?VIVS_RS_CONFIG_FLIP:0));
- SET_STATE(RS_SOURCE_ADDR, rs->source_addr);
- SET_STATE(RS_PIPE_SOURCE_ADDR[0], rs->source_addr);
- SET_STATE(RS_PIPE_SOURCE_ADDR[1], rs->source_addr); /* TODO */
- SET_STATE(RS_SOURCE_STRIDE, (rs->source_stride << source_stride_shift) | ((rs->source_tiling&2)?VIVS_RS_SOURCE_STRIDE_TILING:0));
- SET_STATE(RS_DEST_ADDR, rs->dest_addr);
- SET_STATE(RS_PIPE_DEST_ADDR[0], rs->dest_addr);
- SET_STATE(RS_PIPE_DEST_ADDR[1], rs->dest_addr); /* TODO */
- SET_STATE(RS_DEST_STRIDE, (rs->dest_stride << dest_stride_shift) | ((rs->dest_tiling&2)?VIVS_RS_DEST_STRIDE_TILING:0));
+ SET_STATE(RS_SOURCE_ADDR, rs->source_addr[0]);
+ SET_STATE(RS_PIPE_SOURCE_ADDR[0], rs->source_addr[0]);
+ SET_STATE(RS_SOURCE_STRIDE, (rs->source_stride << source_stride_shift) |
+ ((rs->source_tiling&2)?VIVS_RS_SOURCE_STRIDE_TILING:0) |
+ ((source_multi)?VIVS_RS_SOURCE_STRIDE_MULTI:0));
+ SET_STATE(RS_DEST_ADDR, rs->dest_addr[0]);
+ SET_STATE(RS_PIPE_DEST_ADDR[0], rs->dest_addr[0]);
+ SET_STATE(RS_DEST_STRIDE, (rs->dest_stride << dest_stride_shift) |
+ ((rs->dest_tiling&2)?VIVS_RS_DEST_STRIDE_TILING:0) |
+ ((dest_multi)?VIVS_RS_DEST_STRIDE_MULTI:0));
if (ctx->conn->chip.pixel_pipes == 1)
{
SET_STATE(RS_WINDOW_SIZE, VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) | VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height));
}
else if (ctx->conn->chip.pixel_pipes == 2)
{
+ if (source_multi)
+ {
+ SET_STATE(RS_PIPE_SOURCE_ADDR[1], rs->source_addr[1]);
+ }
+ if (dest_multi)
+ {
+ SET_STATE(RS_PIPE_DEST_ADDR[1], rs->dest_addr[1]);
+ }
SET_STATE(RS_WINDOW_SIZE, VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) | VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2));
}
SET_STATE(RS_PIPE_OFFSET[0], VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(0));
@@ -92,6 +112,18 @@ void etna_compile_rs_state(struct etna_ctx *restrict ctx, struct compiled_rs_sta
SET_STATE(RS_FILL_VALUE[2], rs->clear_value[2]);
SET_STATE(RS_FILL_VALUE[3], rs->clear_value[3]);
SET_STATE(RS_EXTRA_CONFIG, VIVS_RS_EXTRA_CONFIG_AA(rs->aa) | VIVS_RS_EXTRA_CONFIG_ENDIAN(rs->endian_mode));
+
+#ifdef DEBUG
+ printf("cs->dest_addr1: 0x%08x\n", cs->RS_PIPE_DEST_ADDR[0]);
+ printf("cs->dest_addr2: 0x%08x\n", cs->RS_PIPE_DEST_ADDR[1]);
+ printf("cs->source_addr1 0x%08x\n", cs->RS_PIPE_SOURCE_ADDR[0]);
+ printf("cs->source_addr2: 0x%08x\n", cs->RS_PIPE_SOURCE_ADDR[1]);
+ printf("rs->dest_tiling: 0x%08x\n", rs->dest_tiling);
+ printf("rs->source_tiling: 0x%08x\n", rs->source_tiling);
+ printf("cs->dest_stride: 0x%08x\n", cs->RS_DEST_STRIDE);
+ printf("cs->source_stride: 0x%08x\n", cs->RS_SOURCE_STRIDE);
+ printf("\n");
+#endif
}
/* submit RS state, without any processing and no dependence on context
@@ -126,21 +158,37 @@ void etna_submit_rs_state(struct etna_ctx *restrict ctx, const struct compiled_r
}
else if (ctx->conn->chip.pixel_pipes == 2)
{
- etna_reserve(ctx, 34);
+ etna_reserve(ctx, 34); /* worst case - both pipes multi=1 */
/*0 */ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_CONFIG>>2, 1, 0);
/*1 */ ETNA_EMIT(ctx, cs->RS_CONFIG);
/*2 */ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_SOURCE_STRIDE>>2, 1, 0);
/*3 */ ETNA_EMIT(ctx, cs->RS_SOURCE_STRIDE);
/*4 */ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_DEST_STRIDE>>2, 1, 0);
/*5 */ ETNA_EMIT(ctx, cs->RS_DEST_STRIDE);
- /*6 */ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_PIPE_SOURCE_ADDR(0)>>2, 2, 0);
- /*7 */ ETNA_EMIT(ctx, cs->RS_PIPE_SOURCE_ADDR[0]);
- /*8 */ ETNA_EMIT(ctx, cs->RS_PIPE_SOURCE_ADDR[1]);
- /*9 */ ETNA_EMIT(ctx, 0x00000000); /* pad */
- /*10*/ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_PIPE_DEST_ADDR(0)>>2, 2, 0);
- /*11*/ ETNA_EMIT(ctx, cs->RS_PIPE_DEST_ADDR[0]);
- /*12*/ ETNA_EMIT(ctx, cs->RS_PIPE_DEST_ADDR[1]);
- /*13*/ ETNA_EMIT(ctx, 0x00000000); /* pad */
+ if (cs->RS_SOURCE_STRIDE & VIVS_RS_SOURCE_STRIDE_MULTI)
+ {
+ /*6 */ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_PIPE_SOURCE_ADDR(0)>>2, 2, 0);
+ /*7 */ ETNA_EMIT(ctx, cs->RS_PIPE_SOURCE_ADDR[0]);
+ /*8 */ ETNA_EMIT(ctx, cs->RS_PIPE_SOURCE_ADDR[1]);
+ /*9 */ ETNA_EMIT(ctx, 0x00000000); /* pad */
+ }
+ else
+ {
+ /*6 */ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_PIPE_SOURCE_ADDR(0)>>2, 1, 0);
+ /*7 */ ETNA_EMIT(ctx, cs->RS_PIPE_SOURCE_ADDR[0]);
+ }
+ if (cs->RS_DEST_STRIDE & VIVS_RS_DEST_STRIDE_MULTI)
+ {
+ /*10*/ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_PIPE_DEST_ADDR(0)>>2, 2, 0);
+ /*11*/ ETNA_EMIT(ctx, cs->RS_PIPE_DEST_ADDR[0]);
+ /*12*/ ETNA_EMIT(ctx, cs->RS_PIPE_DEST_ADDR[1]);
+ /*13*/ ETNA_EMIT(ctx, 0x00000000); /* pad */
+ }
+ else
+ {
+ /*10 */ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_PIPE_DEST_ADDR(0)>>2, 1, 0);
+ /*11 */ ETNA_EMIT(ctx, cs->RS_PIPE_DEST_ADDR[0]);
+ }
/*14*/ ETNA_EMIT_LOAD_STATE(ctx, VIVS_RS_PIPE_OFFSET(0)>>2, 2, 0);
/*15*/ ETNA_EMIT(ctx, cs->RS_PIPE_OFFSET[0]);
/*16*/ ETNA_EMIT(ctx, cs->RS_PIPE_OFFSET[1]);
diff --git a/src/etnaviv/etna_rs.h b/src/etnaviv/etna_rs.h
index b660a10..a4b26c0 100644
--- a/src/etnaviv/etna_rs.h
+++ b/src/etnaviv/etna_rs.h
@@ -36,9 +36,9 @@ struct rs_state
uint8_t dest_format; // RS_FORMAT_XXX
uint8_t swap_rb;
uint8_t flip;
- uint32_t source_addr;
+ uint32_t source_addr[2];
uint32_t source_stride;
- uint32_t dest_addr;
+ uint32_t dest_addr[2];
uint32_t dest_stride;
uint16_t width; // source width
uint16_t height; // source height
diff --git a/src/lib/fbdemos.c b/src/lib/fbdemos.c
index 3d3d55b..c8a9128 100644
--- a/src/lib/fbdemos.c
+++ b/src/lib/fbdemos.c
@@ -292,7 +292,8 @@ int etna_fb_bind_resource(struct fbdemos_scaffold *fbs, struct pipe_resource *rt
etna_compile_rs_state(fbs->ctx, &fb->copy_to_screen[bi], &(struct rs_state){
.source_format = translate_rt_format(rt_resource->base.format, false),
.source_tiling = rt_resource->layout,
- .source_addr = etna_bo_gpu_address(rt_resource->bo) + rt_resource->levels[0].offset,
+ .source_addr[0] = rt_resource->pipe_addr[0],
+ .source_addr[1] = rt_resource->pipe_addr[1],
.source_stride = rt_resource->levels[0].stride,
.dest_format = fb->rs_format,
.dest_tiling = ETNA_LAYOUT_LINEAR,
generated by cgit (git 2.34.1) at 2025-05-10 01:38:34 +0000