path: root/rnndb/state.xml

<?xml version="1.0" encoding="UTF-8"?>
<!-- Copyright (c) 2012-2013 The Etnaviv Project

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<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<!-- Vivante GCxxxx render states and registers overview:
     Main part (frontend and global)
 -->
<!--
     Registers and render states live in the same address space, although some
     can only be accessed through the kernel register interface and others only through
     state-modifying commands (TODO: figure out which ones).

     To use the 2D engine, the pipe should be set to PIPE_2D and to use the 3D
     engine, the pipe should be set to PIPE_3D.

     This file is in Envytools rules-ng-ng format with the following extensions:

         - regXX attribute "value": initial state value in new context
         - attribute "brief": short human-friendly name of this register/array, can be an attribute as well as <brief>;
                                   <doc> is left for longer specific documentation
         - type="fixedp": (N/2).(N/2) fixed-point value, where N is the number of bits of the bit field,
             so in case of a 32 bit field it will be a 16.16 FP value.
         - domains can be used as types (to signify a memory address in that domain)
         - for registers: masked="yes", defaults to "no" to mark registers that support partial
           state writes by using masks per bit group (mask for state group A must be called A_MASK)

     TODO: variants are somewhat different from NV; what features are supported is determined by (most common first)
         1) Chip (minor) feature flags
         2) Chip specs (number of instructions, pipelines, ...)
         3) Chip model (GC800, GC2000, ...)
         4) Chip revision of the form 0x1234

         Generally the chip feature flags are used to distinguish functionality, as well as the specs, and not the model
         and revision. Unlike NV which parametrizes everything on the model, for GC this is done only for bugfixes.
-->
<domain name="VIVM" brief="GPU memory domain">
</domain>

<import file="common.xml"/>
<import file="state_hi.xml"/>
<import file="state_2d.xml"/>
<import file="state_3d.xml"/>
<import file="state_vg.xml"/>

<domain name="VIVS" brief="GPU state">

    <!-- Other generic enums -->
    <enum name="VARYING_COMPONENT_USE">
        <value value="0" name="UNUSED" brief="Component is not used"/>
        <value value="1" name="USED" brief="Component is used"/>
        <value value="2" name="POINTCOORD_X" brief="glPointCoord.x"/>
        <value value="3" name="POINTCOORD_Y" brief="glPointCoord.y"/>
    </enum>

    <bitset name="FE_VERTEX_STREAM_CONTROL">
        <bitfield high="7" low="0" name="VERTEX_STRIDE"/>
    </bitset>

    <!-- State ranges -->
    <stripe name="FE" brief="Fetch Engine"> <!-- Also known as Front End or DMA engine -->
        <doc>DMA engine. This is the frontend from the CPU to the GPU, and
            takes care of parsing the command stream and loading states, as well as loading
            vertex streams.</doc>
        <reg32 offset="0x00600" name="VERTEX_ELEMENT_CONFIG" value="0x00000000" length="16" stride="4">
            <!-- length="attrCount" where attrCount, the number of attributes,
                 is 16 if chipMinorFeatures1 bit 23 set, otherwise 12.
             -->
            <bitfield high="3" low="0" name="TYPE" brief="Data type">
                <value value="0" name="BYTE"/>
                <value value="1" name="UNSIGNED_BYTE"/>
                <value value="2" name="SHORT"/>
                <value value="3" name="UNSIGNED_SHORT"/>
                <value value="4" name="INT"/>
                <value value="5" name="UNSIGNED_INT"/>
                <value value="8" name="FLOAT"/>
                <value value="9" name="HALF_FLOAT"/>
                <value value="11" name="FIXED" brief="16.16 fixed point"/>
                <value value="12" name="INT_10_10_10_2"/>
                <value value="13" name="UNSIGNED_INT_10_10_10_2"/>
            </bitfield>
            <bitfield high="5" low="4" name="ENDIAN" type="ENDIAN_MODE"/>
            <bitfield pos="7" name="NONCONSECUTIVE" brief="Enable when this is not consecutive to next element, or it is the last element"/>
            <bitfield high="10" low="8" name="STREAM" brief="Source stream number"/>
            <bitfield high="13" low="12" name="NUM" brief="Number of elements">
                <doc>Wraps around (1=1,2=2,3=3,4=0)</doc>
            </bitfield>
            <bitfield high="15" low="14" name="NORMALIZE" brief="Normalize to 0..1">
                <value value="0" name="OFF"/>
                <value value="2" name="ON"/>
            </bitfield>
            <bitfield high="23" low="16" name="START" brief="Starting offset of element data"/>
            <bitfield high="31" low="24" name="END" brief="End offset of element data minus start of this consecutive stretch"/>
        </reg32>
        <reg32 offset="0x00640" name="CMD_STREAM_BASE_ADDR"/>
        <reg32 offset="0x00644" name="INDEX_STREAM_BASE_ADDR" value="0x00000000" type="VIVM"/>
        <reg32 offset="0x00648" name="INDEX_STREAM_CONTROL" value="0x00000000">
            <bitfield high="1" low="0" name="TYPE">
                <value value="0" name="UNSIGNED_CHAR" brief="8-bit indices"/>
                <value value="1" name="UNSIGNED_SHORT" brief="16-bit indices"/>
                <value value="2" name="UNSIGNED_INT" brief="32-bit indices"/>
            </bitfield>
        </reg32>
        <reg32 offset="0x0064C" name="VERTEX_STREAM_BASE_ADDR" value="0x00000000" type="VIVM"/> <!-- streamCount == 1 -->
        <reg32 offset="0x00650" name="VERTEX_STREAM_CONTROL" value="0x00000000" type="FE_VERTEX_STREAM_CONTROL"/> <!-- streamCount == 1 -->
        <reg32 offset="0x00654" name="COMMAND_ADDRESS" brief="Base address for the command buffer">
            <doc>The address must be 64-bit aligned and it is always physical. This register cannot be read.</doc>
        </reg32>
        <reg32 offset="0x00658" name="COMMAND_CONTROL">
            <bitfield high="15" low="0" name="PREFETCH" brief="Number of 64-bit words to fetch from the command buffer"/>
            <bitfield pos="16" name="ENABLE" brief="Enable the command parser"/>
        </reg32>
        <reg32 offset="0x0065C" name="DMA_STATUS"/>
        <reg32 offset="0x00660" name="DMA_DEBUG_STATE" brief="DMA debug status">
            <bitfield high="4" low="0" name="CMD_STATE" brief="Command state">
                <value value="0" name="IDLE"/>
                <value value="1" name="DEC"/>
                <value value="2" name="ADR0"/>
                <value value="3" name="LOAD0"/>
                <value value="4" name="ADR1"/>
                <value value="5" name="LOAD1"/>
                <value value="6" name="3DADR"/>
                <value value="7" name="3DCMD"/>
                <value value="8" name="3DCNTL"/>
                <value value="9" name="3DIDXCNTL"/>
                <value value="10" name="INITREQDMA"/>
                <value value="11" name="DRAWIDX"/>
                <value value="12" name="DRAW"/>
                <value value="13" name="2DRECT0"/>
                <value value="14" name="2DRECT1"/>
                <value value="15" name="2DDATA0"/>
                <value value="16" name="2DDATA1"/>
                <value value="17" name="WAITFIFO"/>
                <value value="18" name="WAIT"/>
                <value value="19" name="LINK"/>
                <value value="20" name="END"/>
                <value value="21" name="STALL"/>
            </bitfield>
            <bitfield high="9" low="8" name="CMD_DMA_STATE" brief="Command DMA state">
                <value value="0" name="IDLE"/>
                <value value="1" name="START"/>
                <value value="2" name="REQ"/>
                <value value="3" name="END"/>
            </bitfield>
            <bitfield high="11" low="10" name="CMD_FETCH_STATE" brief="Command fetch state">
                <value value="0" name="IDLE"/>
                <value value="1" name="RAMVALID"/>
                <value value="2" name="VALID"/>
            </bitfield>
            <bitfield high="13" low="12" name="REQ_DMA_STATE" brief="DMA request state">
                <value value="0" name="IDLE"/>
                <value value="1" name="WAITIDX"/>
                <value value="2" name="CAL"/>
            </bitfield>
            <bitfield high="15" low="14" name="CAL_STATE" brief="Cal state">
                <value value="0" name="IDLE"/>
                <value value="1" name="LDADR"/>
                <value value="2" name="IDXCALC"/>
            </bitfield>
            <bitfield high="17" low="16" name="VE_REQ_STATE" brief="VE request state">
                <value value="0" name="IDLE"/>
                <value value="1" name="CKCACHE"/>
                <value value="2" name="MISS"/>
            </bitfield>
        </reg32>
        <reg32 offset="0x00664" name="DMA_ADDRESS" brief="The current command decoder address (r/o)">
            <doc>This is useful for debugging a stuck command queue.</doc>
        </reg32>
        <reg32 offset="0x00668" name="DMA_LOW" brief="FE fetched word 0">
            <doc>
                The GPU's DMA engine fetches 64-bit words at once. This register will read the lower
                32 bits (word 0) of the last-fetched DMA word.
            </doc>
        </reg32>
        <reg32 offset="0x0066C" name="DMA_HIGH" brief="FE fetched word 1">
            <doc>
                The GPU's DMA engine fetches 64-bit words at once. This register will read the upper
                32 bits (word 1) of the last-fetched DMA word.
            </doc>
        </reg32>
        <reg32 offset="0x00670" name="AUTO_FLUSH" value="0x00000000" brief="Auto flush cycles"/>
        <reg32 offset="0x00678" name="UNK00678" value="0x00000000"/>
        <reg32 offset="0x0067C" name="UNK0067C" value="0xFFFFFFFF"/>
        <stripe name="VERTEX_STREAMS" length="8" stride="4"> <!-- streamCount > 1 -->
            <reg32 offset="0x00680" name="BASE_ADDR" value="0x00000000" type="VIVM"/>
            <reg32 offset="0x006A0" name="CONTROL" value="0x00000000" type="FE_VERTEX_STREAM_CONTROL"/>
        </stripe>
        <reg32 offset="0x00700" name="UNK00700" value="0x00000000" length="16" stride="4"/>
        <reg32 offset="0x00740" name="UNK00740" value="0x00000000" length="16" stride="4"/>
        <reg32 offset="0x00780" name="UNK00780" value="0x3F800000" length="16" stride="4"/>
    </stripe>

    <stripe name="GL" brief="Global states">
        <doc>Global device control states. Here is configured what pipe to use (2D or 3D),
            when to send event, when to wait on semaphores and the API mode (OGL or D3D).
        </doc>
        <reg32 offset="0x03800" name="PIPE_SELECT" brief="Select the current graphics pipe">
            <doc>Make sure that the PE is idle before switching pipes.</doc>
            <bitfield pos="0" name="PIPE" type="PIPE_ID"/>
        </reg32>
        <reg32 offset="0x03804" name="EVENT" brief="Send an event">
            <bitfield high="4" low="0" name="EVENT_ID"/>
            <bitfield pos="5" name="FROM_FE"/>
            <bitfield pos="6" name="FROM_PE"/>
            <bitfield high="12" low="8" name="SOURCE" brief="Event source (GC320)"/>
        </reg32>
        <reg32 offset="0x03808" name="SEMAPHORE_TOKEN" brief="A sempahore state arms the semaphore in the destination">
            <bitfield high="4" low="0" name="FROM" type="SYNC_RECIPIENT"/>
            <bitfield high="12" low="8" name="TO" type="SYNC_RECIPIENT"/>
        </reg32>
        <reg32 offset="0x0380C" name="FLUSH_CACHE" brief="Flush the current pipe">
            <bitfield pos="0" name="DEPTH"/>
            <bitfield pos="1" name="COLOR"/>
            <bitfield pos="2" name="TEXTURE"/>
            <bitfield pos="3" name="PE2D" brief="Flush the 2D pixel cache"/>
            <bitfield pos="4" name="TEXTUREVS">
                <doc>
                Warning: setting the `TEXTUREVS` bit seems to result in crashes when rendering directly afterwards.
                Even adding a PE to FE semaphore afterwards or dummy state loads does not fix this.
                </doc>
            </bitfield>
            <bitfield pos="5" name="SHADER_L1"/>
            <bitfield pos="6" name="SHADER_L2"/>
        </reg32>
        <reg32 offset="0x03810" name="FLUSH_MMU" brief="Flush the virtual address lookup cache inside the MC">
            <bitfield pos="0" name="FLUSH_FEMMU" brief="Flush the FE address translation caches"/>
            <bitfield pos="1" name="FLUSH_PEMMU" brief="Flush the PE render target address translation caches"/>
        </reg32>
        <reg32 offset="0x03814" name="VERTEX_ELEMENT_CONFIG" value="0x00000001"/>
        <reg32 offset="0x03818" name="MULTI_SAMPLE_CONFIG" value="0x00000000" masked="yes">
            <bitfield high="1" low="0" name="MSAA_SAMPLES">
                <value value="0" name="NONE"/>
                <value value="1" name="2X"/>
                <value value="2" name="4X"/>
            </bitfield>
            <bitfield pos="3" name="MSAA_SAMPLES_MASK"/>
            <bitfield high="7" low="4" name="MSAA_ENABLES"/>
            <bitfield pos="8" name="MSAA_ENABLES_MASK"/>
            <bitfield high="14" low="12" name="UNK12"/>
            <bitfield pos="15" name="UNK12_MASK"/>
            <bitfield high="17" low="16" name="UNK16"/>
            <bitfield pos="19" name="UNK16_MASK"/>
        </reg32>
        <reg32 offset="0x0381C" name="VARYING_TOTAL_COMPONENTS" brief="Total number of components in all varyings" value="0x00000000">
            <doc>Number of components for all varyings together, rounded to a multiple of 2.</doc>
            <bitfield high="7" low="0" name="NUM"/>
        </reg32>
        <reg32 offset="0x03820" name="VARYING_NUM_COMPONENTS" brief="Number of components in varyings" value="0x00000000">
            <doc>Number of components per varying (PS).</doc>
            <bitfield high="2" low="0" name="VAR0"/>
            <bitfield high="6" low="4" name="VAR1"/>
            <bitfield high="10" low="8" name="VAR2"/>
            <bitfield high="14" low="12" name="VAR3"/>
            <bitfield high="18" low="16" name="VAR4"/>
            <bitfield high="22" low="20" name="VAR5"/>
            <bitfield high="26" low="24" name="VAR6"/>
            <bitfield high="30" low="28" name="VAR7"/>
        </reg32>
        <reg32 offset="0x03828" name="VARYING_COMPONENT_USE" brief="Varying component usage" value="0x00000000" length="2" stride="4">
            <doc>2 bits per varying component, 16 components per 32-bit word.</doc>
            <bitfield high="1" low="0" name="COMP0" type="VARYING_COMPONENT_USE"/>
            <bitfield high="3" low="2" name="COMP1" type="VARYING_COMPONENT_USE"/>
            <bitfield high="5" low="4" name="COMP2" type="VARYING_COMPONENT_USE"/>
            <bitfield high="7" low="6" name="COMP3" type="VARYING_COMPONENT_USE"/>
            <bitfield high="9" low="8" name="COMP4" type="VARYING_COMPONENT_USE"/>
            <bitfield high="11" low="10" name="COMP5" type="VARYING_COMPONENT_USE"/>
            <bitfield high="13" low="12" name="COMP6" type="VARYING_COMPONENT_USE"/>
            <bitfield high="15" low="14" name="COMP7" type="VARYING_COMPONENT_USE"/>
            <bitfield high="17" low="16" name="COMP8" type="VARYING_COMPONENT_USE"/>
            <bitfield high="19" low="18" name="COMP9" type="VARYING_COMPONENT_USE"/>
            <bitfield high="21" low="20" name="COMP10" type="VARYING_COMPONENT_USE"/>
            <bitfield high="23" low="22" name="COMP11" type="VARYING_COMPONENT_USE"/>
            <bitfield high="25" low="24" name="COMP12" type="VARYING_COMPONENT_USE"/>
            <bitfield high="27" low="26" name="COMP13" type="VARYING_COMPONENT_USE"/>
            <bitfield high="29" low="28" name="COMP14" type="VARYING_COMPONENT_USE"/>
            <bitfield high="31" low="30" name="COMP15" type="VARYING_COMPONENT_USE"/>
        </reg32>
        <reg32 offset="0x03834" name="UNK03834" value="0x00000000"/>
        <reg32 offset="0x03838" name="UNK03838" value="0x00000000"/>
        <reg32 offset="0x0384C" name="API_MODE" brief="API mode" value="0x00000000">
            <value value="0" name="OPENGL"/>
            <value value="1" name="OPENVG"/>
            <value value="2" name="OPENCL"/>
        </reg32>
        <reg32 offset="0x03850" name="CONTEXT_POINTER" brief="Context token"> <!-- DEBUG -->
            <doc>
            The current context pointer is stored here by the v4 kernel driver if debugging is enabled.
            Likely this register is not used by the hardware, but only by debugging software.
            </doc>
        </reg32>
        <reg32 offset="0x03A00" name="UNK03A00"/>
        <reg32 offset="0x03C00" name="STALL_TOKEN">
            <bitfield high="4" low="0" name="FROM" type="SYNC_RECIPIENT"/>
            <bitfield high="12" low="8" name="TO" type="SYNC_RECIPIENT"/>
            <bitfield pos="30" name="FLIP0"/>
            <bitfield pos="31" name="FLIP1"/>
        </reg32>
    </stripe>

    <stripe name="DUMMY" brief="/dev/null">
        <doc>Dummy state write, sometimes used for inserting padding or small delays into the command stream.</doc>
        <reg32 offset="0x3FFFC" name="DUMMY"/>
    </stripe>
</domain>

</database>