arm64: dts: add SolidRun CN9130 Clearfog Base dtsclearfog

Add support for the CN9130 SOM attached to a Clearfog Base platform.
This is similar to the Armada 388 based Clearfog Base platform.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

3 files changed, 80 insertions, 12 deletions

diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index ce751b5028e2..700e6752c5fb 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
index 788a5c302b17..ebc45b3d2a48 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
@@ -52,7 +52,7 @@
 	};
 };
 
-/* SRDS #3 - SGMII 1GE */
+/* SRDS #3 - SGMII 1GE on carrier board */
 &cp0_eth1 {
 	phy = <&phy1>;
 	phys = <&cp0_comphy3 1>;
@@ -111,6 +111,7 @@
 		 * - on-state: low
 		 * - off-state: high (not hi-z, to avoid residual glow)
 		 */
+		/* marvell,reg-init = <3 16 0 0x0064>; */
 		marvell,reg-init = <3 16 0xf000 0x0a61>,
 				   <3 17 0x003f 0x000a>;
 
@@ -136,8 +137,10 @@
 };
 
 &cp0_pinctrl {
-	pinctrl-0 = <&sim_select_pins>;
-	pintrl-names = "default";
+	expander0_pins: cp0-expander0-pins {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
 
 	rear_button_pins: cp0-rear-button-pins {
 		marvell,pins = "mpp31";
@@ -162,6 +165,11 @@
 };
 
 &expander0 {
+	pinctrl-0 = <&expander0_pins>;
+	pinctrl-names = "default";
+	interrupt-parent = <&cp0_gpio1>;
+	interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+
 	m2-full-card-power-off-hog {
 		gpio-hog;
 		gpios = <2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
index ad0ab34b6602..49d5d9111454 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
@@ -6,6 +6,8 @@
  *
  */
 
+#include <dt-bindings/input/input.h>
+
 / {
 	aliases {
 		/* label nics same order as armada 388 clearfog */
@@ -16,6 +18,14 @@
 		mmc1 = &cp0_sdhci0;
 	};
 
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
 	reg_usb3_vbus0: regulator-usb3-vbus0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vbus0";
@@ -33,6 +43,23 @@
 		tx-fault-gpios = <&expander0 13 GPIO_ACTIVE_HIGH>;
 		maximum-power-milliwatt = <2000>;
 	};
+
+	rfkill-gnss {
+		compatible = "rfkill-gpio";
+		label = "m.2 GNSS";
+		radio-type = "gps";
+		/* rfkill-gpio inverts internally */
+		shutdown-gpios = <&expander0 9 GPIO_ACTIVE_HIGH>;
+	};
+
+	/* M.2 is B-keyed, so w-disable is for WWAN */
+	rfkill-wwan {
+		compatible = "rfkill-gpio";
+		label = "m.2 WWAN";
+		radio-type = "wwan";
+		/* rfkill-gpio inverts internally */
+		shutdown-gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+	};
 };
 
 /* SRDS #2 - SFP+ 10GE */
@@ -60,15 +87,23 @@
 			gpio-hog;
 			gpios = <0 GPIO_ACTIVE_LOW>;
 			input;
-			line-name = "pcie2.0-clkreq";
+			line-name = "pcie1.0-clkreq";
+		};
+
+		m2-ful-card-power-off {
+			gpio-hog;
+			gpios = <2 GPIO_ACTIVE_HIGH>;
+			output-high;
+			line-name = "m2-ful-card-power-off";
 		};
 
 		/* CON3 */
+		/* mini-PCIe can be either WWAN or WLAN */
 		pcie2-0-w-disable-hog {
 			gpio-hog;
 			gpios = <3 GPIO_ACTIVE_LOW>;
 			output-low;
-			line-name = "pcie2.0-w-disable";
+			line-name = "pcie1.0-w-disable";
 		};
 
 		usb3-ilimit-hog {
@@ -78,6 +113,20 @@
 			line-name = "usb3-current-limit";
 		};
 
+		usb3-power-hog {
+			gpio-hog;
+			gpios = <6 GPIO_ACTIVE_HIGH>;
+			output-high;
+			line-name = "usb3-power";
+		};
+
+		m2-reset-hog {
+			gpio-hog;
+			gpios = <10 GPIO_ACTIVE_HIGH>;
+			output-high;
+			line-name = "m.2 reset";
+		};
+
 		m2-devslp-hog {
 			gpio-hog;
 			gpios = <11 GPIO_ACTIVE_HIGH>;
@@ -108,7 +157,7 @@
 	 * PCIe uses ARP to assign addresses, or 0x63-0x64.
 	 */
 	clock-frequency = <100000>;
-	pinctrl-0 = <&cp0_i2c1_pins>;
+	pinctrl-0 = <&clearfog_i2c1_pins>;
 	pinctrl-names = "default";
 	status = "okay";
 };
@@ -123,7 +172,7 @@
 };
 
 &cp0_pinctrl {
-	cp0_i2c1_pins: cp0-i2c1-pins {
+	clearfog_i2c1_pins: cp0-i2c1-pins {
 		marvell,pins = "mpp35", "mpp36";
 		marvell,function = "i2c1";
 	};
@@ -161,10 +210,13 @@
 
 /* microSD */
 &cp0_sdhci0 {
+	cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
 	pinctrl-0 = <&cp0_mmc0_pins>;
 	pinctrl-names = "default";
 	bus-width = <4>;
 	no-1-8-v;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
 	status = "okay";
 };
 
@@ -173,6 +225,13 @@
 	pinctrl-0 = <&cp0_spi1_pins &mikro_spi_pins>;
 };
 
+/* mikrobus uart */
+&cp0_uart0 {
+	pinctrl-0 = <&mikro_uart_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 /*
  * SRDS #1 - USB-3.0 Host on Type-A connector
  * USB-2.0 Host on mPCI-e connector (CON3)
@@ -185,13 +244,13 @@
 	status = "okay";
 };
 
-&cp0_utmi {
+/* SRDS #4 - M.2 USB 3.0 */
+&cp0_usb3_1 {
+	phy-names = "usb";
+	phys = <&cp0_comphy4 1>;
 	status = "okay";
 };
 
-/* mikrobus uart */
-&cp0_uart0 {
-	pinctrl-0 = <&mikro_uart_pins>;
-	pinctrl-names = "default";
+&cp0_utmi {
 	status = "okay";
 };