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authorPaul Kocialkowski <paulk@sys-base.io>2025-07-01 22:11:23 +0200
committerChen-Yu Tsai <wens@csie.org>2025-07-03 23:31:05 +0800
commit01fdcbc7e5a56c9cba521e0f237cb5c3fd162432 (patch)
tree68c7002389b04b9031c6061bc34188c3acaac675
parent2b73328629396d32e41ca1f023653b07abf2b42f (diff)
clk: sunxi-ng: v3s: Fix TCON clock parents
The TCON clock can be parented to both the video PLL and the periph0 PLL. Add the latter, which was missing from the list. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Link: https://patch.msgid.link/20250701201124.812882-5-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-v3s.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 86d933d1ac72..52e4369664c5 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -350,7 +350,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
-static const char * const tcon_parents[] = { "pll-video" };
+static const char * const tcon_parents[] = { "pll-video", "pll-periph0" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
0x118, 0, 4, 24, 3, BIT(31), 0);