diff options
| author | Russell King <rmk+kernel@armlinux.org.uk> | 2021-02-02 13:45:28 +0000 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-04-04 14:59:10 +0100 |
| commit | 2f53b6b204b4833731c57467ef1086fef04699b2 (patch) | |
| tree | 1f22877982f27a1466e1ee145a4ca58dc74c0da4 | |
| parent | 01d952fbec863a73726ce007b125b1eb906fac63 (diff) | |
PCI: pci-bridge-emul: re-arrange register tests
Re-arrange the tests for which sets of registers are being accessed
so that it is easier to add further regions later. No functional
change.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
| -rw-r--r-- | drivers/pci/pci-bridge-emul.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c index 6658c1edd464..15013d91992a 100644 --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -477,8 +477,11 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, read_op = pci_bridge_emul_read_ssid; cfgspace = NULL; behavior = NULL; - } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF && - bridge->has_pcie) { + } else if (!bridge->has_pcie) { + /* PCIe space is not implemented, and no PCI capabilities */ + *value = 0; + return PCIBIOS_SUCCESSFUL; + } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF) { /* Our emulated PCIe capability */ reg -= bridge->pcie_start; read_op = bridge->ops->read_pcie; @@ -551,14 +554,16 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, write_op = bridge->ops->write_base; cfgspace = (__le32 *) &bridge->conf; behavior = bridge->pci_regs_behavior; - } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF && - bridge->has_pcie) { + } else if (!bridge->has_pcie) { + /* PCIe space is not implemented, and no PCI capabilities */ + return PCIBIOS_SUCCESSFUL; + } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF) { /* Our emulated PCIe capability */ reg -= bridge->pcie_start; write_op = bridge->ops->write_pcie; cfgspace = (__le32 *) &bridge->pcie_conf; behavior = bridge->pcie_cap_regs_behavior; - } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) { + } else if (reg >= PCI_CFG_SPACE_SIZE) { /* PCIe extended capability space */ reg -= PCI_CFG_SPACE_SIZE; write_op = bridge->ops->write_ext; |