diff options
| author | Jagan Teki <jagan@edgeble.ai> | 2023-11-26 00:35:20 +0530 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2024-01-25 21:28:47 +0100 |
| commit | 92eaee21abbdf07001a7ee3c0d03c48889619600 (patch) | |
| tree | 228dbba359de7ae6d2a6f65d1463a380d61ddf13 | |
| parent | 5d85d4c7e03b44bc31814420bb73b2ba12e42c22 (diff) | |
arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key
Edgeble NCM6A-IO board has M.2 B-Key, E-Key via PCI3x2.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20231125190522.87607-9-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index d04eea158545..05bea1fc6a51 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -19,6 +19,19 @@ vin-supply = <&vcc_3v3_s3>; }; + vcc3v3_pcie3x2: vcc3v3-pcie3x2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_vcc3v3_en>; + regulator-name = "vcc3v3_pcie3x2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -70,6 +83,15 @@ status = "okay"; }; +/* B-Key and E-Key */ +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie3x2>; + status = "okay"; +}; + /* M-Key */ &pcie3x4 { pinctrl-names = "default"; @@ -87,6 +109,14 @@ }; pcie3 { + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en { + rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie3x4_rst: pcie3x4-rst { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; |