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authorJesse.zhang@amd.com <jesse.zhang@amd.com>2025-01-18 17:05:25 +0800
committerAlex Deucher <alexander.deucher@amd.com>2025-01-24 09:54:08 -0500
commit941f0cb6c8609ea5bab095d5deb3fe367cc41c85 (patch)
treeb5cbb1262922de59f353f1860a974347233bced4
parente9b86b841baf2e4e7e8b3521734aeb4803f22b99 (diff)
revert "drm/amdgpu/pm: Implement SDMA queue reset for different asic"
pmfw unified PPSMC_MSG_ResetSDMA definitions for different devices. PPSMC_MSG_ResetSDMA2 is not needed. Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c30
1 files changed, 9 insertions, 21 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 6b8e5c2d7bf5..0338f9cfb514 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2833,29 +2833,17 @@ static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)
static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
{
- uint32_t smu_program;
+ struct amdgpu_device *adev = smu->adev;
int ret = 0;
- smu_program = (smu->smc_fw_version >> 24) & 0xff;
- switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
- case IP_VERSION(13, 0, 6):
- if ((smu_program == 7 || smu_program == 0) &&
- smu_v13_0_6_caps_supported(smu, SMU_CAPS(SDMA_RESET)))
- ret = smu_cmn_send_smc_msg_with_param(smu,
- SMU_MSG_ResetSDMA, inst_mask, NULL);
- else if ((smu_program == 4) &&
- smu_v13_0_6_caps_supported(smu, SMU_CAPS(SDMA_RESET)))
- ret = smu_cmn_send_smc_msg_with_param(smu,
- SMU_MSG_ResetSDMA2, inst_mask, NULL);
- break;
- case IP_VERSION(13, 0, 14):
- if (smu_v13_0_6_caps_supported(smu, SMU_CAPS(SDMA_RESET)))
- ret = smu_cmn_send_smc_msg_with_param(smu,
- SMU_MSG_ResetSDMA2, inst_mask, NULL);
- break;
- default:
- break;
- }
+ /* the message is only valid on SMU 13.0.6 with pmfw 85.121.00 and above */
+ if ((adev->flags & AMD_IS_APU) ||
+ amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 6) ||
+ smu->smc_fw_version < 0x00557900)
+ return 0;
+
+ ret = smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_ResetSDMA, inst_mask, NULL);
if (ret)
dev_err(smu->adev->dev,