diff options
| author | Sascha Bischoff <Sascha.Bischoff@arm.com> | 2025-10-22 13:45:37 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2025-11-13 18:09:46 +0000 |
| commit | a0b130eedde0bc8c2d03932539e6753e2f0f70bc (patch) | |
| tree | 5cc4d3c00085ccbcd2a3855ea5728030e0f1ff7a | |
| parent | fe2ef46995d5db49a37337f11fe2c6733676c24c (diff) | |
arm64/sysreg: Move generation of RES0/RES1/UNKN to function
The RESx and UNKN define generation happens in two places
(EndSysreg and EndSysregFields), and was using nearly identical
code. Split this out into a function, and call that instead, rather
then keeping the dupliated code.
There are no changes to the generated sysregs as part of this change.
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rwxr-xr-x | arch/arm64/tools/gen-sysreg.awk | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk index 5ca81eaac2cb..86860ab672dc 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -66,6 +66,18 @@ function define_field_sign(prefix, reg, field, sign) { define(prefix, reg "_" field "_SIGNED", sign) } +# Print the Res0, Res1, Unkn masks +function define_resx_unkn(prefix, reg, res0, res1, unkn) { + if (res0 != null) + define(prefix, reg "_RES0", "(" res0 ")") + if (res1 != null) + define(prefix, reg "_RES1", "(" res1 ")") + if (unkn != null) + define(prefix, reg "_UNKN", "(" unkn ")") + if (res0 != null || res1 != null || unkn != null) + print "" +} + # Parse a "<msb>[:<lsb>]" string into the global variables @msb and @lsb function parse_bitdef(reg, field, bitdef, _bits) { @@ -143,10 +155,7 @@ $1 == "EndSysregFields" && block_current() == "SysregFields" { if (next_bit >= 0) fatal("Unspecified bits in " reg) - define(prefix, reg "_RES0", "(" res0 ")") - define(prefix, reg "_RES1", "(" res1 ")") - define(prefix, reg "_UNKN", "(" unkn ")") - print "" + define_resx_unkn(prefix, reg, res0, res1, unkn) reg = null res0 = null @@ -201,14 +210,7 @@ $1 == "EndSysreg" && block_current() == "Sysreg" { if (next_bit >= 0) fatal("Unspecified bits in " reg) - if (res0 != null) - define(prefix, reg "_RES0", "(" res0 ")") - if (res1 != null) - define(prefix, reg "_RES1", "(" res1 ")") - if (unkn != null) - define(prefix, reg "_UNKN", "(" unkn ")") - if (res0 != null || res1 != null || unkn != null) - print "" + define_resx_unkn(prefix, reg, res0, res1, unkn) reg = null op0 = null |