diff options
| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2023-09-13 22:09:00 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-10-12 18:42:46 +0530 |
| commit | a4f5f39849f39f62f5d4e88cbb600f95f927003d (patch) | |
| tree | abcd3bdbedc5b121ba28b15da187d35c09bbae88 | |
| parent | 9dbaf381008dfa2fad6225633004f7adb1bac252 (diff) | |
dt-bindings: riscv: Add smstateen entry
Add an entry for the Smstateen extension to the riscv,isa-extensions
property.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/extensions.yaml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..36ff6749fbba 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -128,6 +128,12 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: smstateen + description: | + The standard Smstateen extension for controlling access to CSRs + added by other RISC-V extensions in H/S/VS/U/VU modes and as + ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced |