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| author | Darshan Prajapati <darshan.prajapati@einfochips.com> | 2025-08-25 18:54:22 +0530 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-09-25 08:29:01 +0200 |
| commit | b9607ff0f86ad310f4a5e6ac985b1e89d78fd3ec (patch) | |
| tree | 6245e6aa245fb76b7cc62e129ce37f75075d7b29 | |
| parent | b320789d6883cc00ac78ce83bccbfe7ed58afcf0 (diff) | |
dt-bindings: riscv: Add SiFive P550 CPU compatible
Update Documentation for supporting SiFive P550 based CPU
Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250825132427.1618089-2-pinkesh.vaghela@einfochips.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 1a0cf0702a45..153d0dac57fb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -52,6 +52,7 @@ properties: - sifive,e5 - sifive,e7 - sifive,e71 + - sifive,p550 - sifive,rocket0 - sifive,s7 - sifive,u5 |