diff options
| author | Kaustabh Chakraborty <kauschluss@disroot.org> | 2024-11-01 11:31:10 +0900 |
|---|---|---|
| committer | Inki Dae <inki.dae@samsung.com> | 2024-11-04 10:50:46 +0900 |
| commit | f3cb045e2603e80a1633883423b2621aad77989d (patch) | |
| tree | f00b1a33aa7307cda0a2c66d0e993c64cf6feba1 | |
| parent | d31bbacf783daf1e71fbe5c68df93550c446bf44 (diff) | |
drm/exynos: exynos7_drm_decon: fix ideal_clk by converting it to Hz
The clkdiv values are incorrect as ideal_clk is in kHz and the clock
rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos7_drm_decon.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index e994779694f0..76a3f4b0341d 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx) static u32 decon_calc_clkdiv(struct decon_context *ctx, const struct drm_display_mode *mode) { - unsigned long ideal_clk = mode->clock; + unsigned long ideal_clk = mode->clock * 1000; u32 clkdiv; /* Find the clock divider value that gets us closest to ideal_clk */ |