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authorDaniel Vetter <daniel.vetter@ffwll.ch>2018-12-14 11:27:24 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2018-12-14 11:27:24 +0100
commit272c1a9b493986a95219dce674c49877d98cf90f (patch)
tree8ac5e2d5abe20f662083306408f45874e890cf44 /include
parent2a3c83f5fe0770d13bbb71b23674886ff4111f44 (diff)
parent3b5129b3a7c62fdec9cc69b1b3f20917c36ab5d4 (diff)
Merge tag 'exynos-drm-next-for-v4.21-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
Add configurable plane alpha and pixel blend mode support - This patch series adds configurable plane alpha and pixel blend mode support for FIMD device driver. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Inki Dae <inki.dae@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1544772430-8295-1-git-send-email-inki.dae@samsung.com
Diffstat (limited to 'include')
-rw-r--r--include/video/samsung_fimd.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index d8fc96ed11e9..4ba5efe8d086 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -198,6 +198,7 @@
#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
#define WINCONx_ENWIN (1 << 0)
+#define WINCONx_BLEND_MODE_MASK (0xc2)
#define WINCON0_BPPMODE_MASK (0xf << 2)
#define WINCON0_BPPMODE_SHIFT 2
@@ -211,6 +212,7 @@
#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_LOCALSEL_CAMIF (1 << 23)
+#define WINCON1_ALPHA_MUL (1 << 7)
#define WINCON1_BLD_PIX (1 << 6)
#define WINCON1_BPPMODE_MASK (0xf << 2)
#define WINCON1_BPPMODE_SHIFT 2
@@ -437,6 +439,14 @@
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
/* Blending equation control */
+#define BLENDEQx(_win) (0x244 + ((_win - 1) * 4))
+#define BLENDEQ_ZERO 0x0
+#define BLENDEQ_ONE 0x1
+#define BLENDEQ_ALPHA_A 0x2
+#define BLENDEQ_ONE_MINUS_ALPHA_A 0x3
+#define BLENDEQ_ALPHA0 0x6
+#define BLENDEQ_B_FUNC_F(_x) (_x << 6)
+#define BLENDEQ_A_FUNC_F(_x) (_x << 0)
#define BLENDCON 0x260
#define BLENDCON_NEW_MASK (1 << 0)
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)