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| author | chen gong <curry.gong@amd.com> | 2021-01-29 15:37:45 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-02-02 17:34:56 -0500 |
| commit | ea41bd232f167d6fd6505d54485826148b52e54a (patch) | |
| tree | 7856b5ca21cf47029bfbaf4b186b820838d3683c /lib/mpi/mpi-bit.c | |
| parent | b99a8c8f239d76820bbed33c1a42c381cc1f16db (diff) | |
drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register offsets for VGH
For Vangogh:
The offset of the CGTS_TCC_DISABLE is 0x5006 by calculation.
The offset of the CGTS_USER_TCC_DISABLE is 0x5007 by calculation.
Signed-off-by: chen gong <curry.gong@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'lib/mpi/mpi-bit.c')
0 files changed, 0 insertions, 0 deletions