diff options
| author | Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> | 2024-05-14 11:45:08 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2024-05-27 01:33:16 +0100 |
| commit | 9c84429324ea2b5bc537ef8ec7d3727579d37116 (patch) | |
| tree | f96d1bd888246c12beba0a01e3606620c418b215 /net/lapb | |
| parent | a7ed3a11202d90939a3d00ffcc8cf50703cb7b35 (diff) | |
spi: spi-microchip-core: Add support for GPIO based CS
The SPI "hard" controller within the PolarFire SoC is capable of
handling eight CS lines, but only one CS line is wired. Therefore, use
GPIO descriptors to configure additional CS lines.
Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Link: https://msgid.link/r/20240514104508.938448-4-prajna.rajendrakumar@microchip.com
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'net/lapb')
0 files changed, 0 insertions, 0 deletions