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| author | Jiansong Chen <Jiansong.Chen@amd.com> | 2021-04-19 16:33:22 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-04-20 21:36:28 -0400 |
| commit | 7c49ee9ec54c120a46487b9e4d8172c18f2ea9f6 (patch) | |
| tree | fb3205da933f107c89a6ff46d6f5769557162b73 /net/switchdev/switchdev.c | |
| parent | f9727922fc686a4406bb84a91a671c2f0b615ecd (diff) | |
drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish
dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid,
so follow its registers offset setting.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'net/switchdev/switchdev.c')
0 files changed, 0 insertions, 0 deletions