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| author | Manasi Navare <manasi.d.navare@intel.com> | 2019-03-19 15:18:47 -0700 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2019-03-20 12:08:40 -0700 |
| commit | 7264aebb81d15aa6bbed650c816bba90f026bc35 (patch) | |
| tree | 87baeb769bde7cfd8ec23a2e15b7b416734878c8 /scripts/gdb/linux/lists.py | |
| parent | 6e514e371757a62996881e94dd2a488b3e16d518 (diff) | |
drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro
This patch fixes the PORT_SYNC_MODE_MASTER_SELECT macro
to correctly do the left shifting to set the port sync
master select correctly.
I have tested this fix on ICL.
Fixes: 49edbd49786e ("drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers")
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190319221847.21311-1-manasi.d.navare@intel.com
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions