diff options
| author | George Shen <george.shen@amd.com> | 2022-08-10 22:06:17 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-08-29 17:45:10 -0400 |
| commit | 9af611f29034dd6c9329de06dc98232a5b89b939 (patch) | |
| tree | a1a13eff201e29970481f451323a4e57c55b36b4 /scripts/gdb/linux/timerlist.py | |
| parent | a3c9b4c7a75a66b65b62900e2e9d140e0470cd85 (diff) | |
drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming
[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.
Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-to-1 with
HPO stream encoder instance. This is not always
guaranteed and can result in blackscreen.
[How]
Program the correct dpstreamclk instance with
the correct dtbclk_p source.
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/gdb/linux/timerlist.py')
0 files changed, 0 insertions, 0 deletions
