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| author | Marco Pagani <marpagan@redhat.com> | 2024-02-01 16:57:12 +0100 |
|---|---|---|
| committer | Xu Yilun <yilun.xu@linux.intel.com> | 2024-02-18 18:07:06 +0800 |
| commit | b1a91ca25f15b6d7b311de4465854a5981dee3d3 (patch) | |
| tree | f6bfdc91228e9f54925368ba00c47cc81d801714 /scripts/generate_rust_analyzer.py | |
| parent | c20445be92f79bf1abd2a8c31d566697de9e68b0 (diff) | |
fpga: remove redundant checks for bridge ops
Commit 0d70af3c2530 ("fpga: bridge: Use standard dev_release for class
driver") introduced a check in fpga_bridge_register() that prevents
registering a bridge without ops, making checking on every call
redundant.
Signed-off-by: Marco Pagani <marpagan@redhat.com>
Acked-by: Xu Yilun <yilun.xu@intel.com>
Link: https://lore.kernel.org/r/20240201155713.82898-1-marpagan@redhat.com
Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions