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| author | Chuan Liu <chuan.liu@amlogic.com> | 2024-09-09 18:08:56 +0800 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2024-09-30 11:27:36 +0200 |
| commit | c939154e8417d5e04865ff0e45ec8e78592b262d (patch) | |
| tree | 5570bcbb53ce1cc7c26d6a605b894c70e7fd0c53 /scripts/generate_rust_analyzer.py | |
| parent | eb61a126499019ecd688b2978fd6e1fcdfebe58a (diff) | |
clk: meson: Support PLL with fixed fractional denominators
Some PLLS with fractional multipliers have fractional denominators with
fixed values, instead of the previous "(1 << pll-> frc.width)".
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240909-fix_clk-v3-1-a6d8f6333c04@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions