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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-09 23:56:22 +0100 |
|---|---|---|
| committer | Biju Das <biju.das.jz@bp.renesas.com> | 2025-06-12 19:42:27 +0100 |
| commit | e37a95d01d5acce211da8446fefbd8684c67f516 (patch) | |
| tree | 930f177cddd11c6c16aa006f87d0ddf51fbe2bd0 /scripts/lib/kdoc/kdoc_output.py | |
| parent | 660942f2441df622d527f216009f332151843ce8 (diff) | |
drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range
The VCLK range for Renesas RZ/G2L SoC is 5.803 MHz to 148.5 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.
Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Diffstat (limited to 'scripts/lib/kdoc/kdoc_output.py')
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