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authorRodrigo Vivi <rodrigo.vivi@intel.com>2017-08-29 16:09:07 -0700
committerRodrigo Vivi <rodrigo.vivi@intel.com>2017-08-31 09:26:43 -0700
commit385db982b277a1eb5998b6316a500a2d6d9592b1 (patch)
tree605a6b45b6743e94a905b843eaebbe7b84304cb6 /tools/perf/scripts/python/call-graph-from-sql.py
parent86ebb015fa744dd1e265c9b45ade870ac859a4d5 (diff)
drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
Driver’s CPU access to GTT is via the GTTMMADR BAR. The current HW implementation of that BAR is to only support <= DW (and maybe QW) writes—not 16/32/64B writes that could occur with WC and/or SSE/AVX moves. GTTMMADR must be marked uncacheable (UC). Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry). v2: Get clarification on the reasons and spec is getting updated to reflect it now. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Suggested-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829230907.21363-1-rodrigo.vivi@intel.com
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