diff options
| author | Arkadi Sharshevsky <arkadis@mellanox.com> | 2017-03-28 17:24:11 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-03-28 17:11:54 -0700 |
| commit | 0f630fcbe5409aaab1a29b48434b28f41bc360ff (patch) | |
| tree | c39071828e549a5a1dc337a55cfd855c1b164c8d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 1555d204e743b6956d2be294a317121f6112238d (diff) | |
mlxsw: reg: Add counter fields to RITR register
Update RITR for counter support. This allows adding counters for
ASIC's router ports.
Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions