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| author | Jouni Högander <jouni.hogander@intel.com> | 2025-02-13 08:48:00 +0200 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2025-02-14 08:37:49 +0200 |
| commit | 20d6343bf4576674756067a0c59be49526cad072 (patch) | |
| tree | c0ec58e82fd11935561804f488dadb995f8a520c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 452c3fb857f8fe35544335d336eb6ee379ef9b30 (diff) | |
drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit
We have different approach on how flip is considered being complete. We are
waiting for vblank on DSB and generate interrupt when it happens and this
interrupt is considered as indication of completion -> we definitely do not
want to skip vblank wait.
Also not skipping scanline wait shouldn't cause any problems if we are in
DEEP_SLEEP PIPEDSL register is returning 0 -> evasion does nothing and if
we are not in DEEP_SLEEP evasion works same way as without PSR.
v2: add comment explaining why we are not setting DSB_SKIP_WAITS_EN
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-10-jouni.hogander@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions