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| author | Imre Deak <imre.deak@intel.com> | 2025-02-14 16:19:51 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-02-14 21:39:04 +0200 |
| commit | 76120b3a304aec28fef4910204b81a12db8974da (patch) | |
| tree | 44789ffc53fe7a0e38b21b5bf8fbd39b813a18f7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | bccb18c5617a8fb7f6cb2b6d93ae6f2657842929 (diff) | |
drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.
Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions