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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-09-30 15:22:15 +0200 |
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committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-17 14:53:14 +0900 |
commit | 8e1c3aa30c2c3a5f982da9365a1ef03a3ac7a815 (patch) | |
tree | 55f4980518428c6efe25f24bedb2d2cd9f88b1c5 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | a528b4bf1a2ecb756aa65548fd5518fe82fb4648 (diff) |
arm64: dts: r8a7795: Add CA53 L2 cache-controller node
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions