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| author | Jouni Högander <jouni.hogander@intel.com> | 2025-02-13 08:48:03 +0200 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2025-02-14 08:37:50 +0200 |
| commit | ac76a51ddb5efb875c7c9ca87e002ff0aa4f63d1 (patch) | |
| tree | da6ecaf3ec97311267cc24e557802b11c242c7c2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | fa27fa48061afda49f939fcac6c480f0c4c1fcfd (diff) | |
drm/i915/display: Ensure we have "Frame Change" event in DSB commit
We may have commit which doesn't have any non-arming plane register
writes. In that case there aren't "Frame Change" event before DSB vblank
evasion which hangs as PIPEDSL register is reading as 0 when PSR state is
SRDENT(PSR1) or DEEP_SLEEP(PSR2). Handle this by ensuring "Frame Change"
event at the begin of DSB commit if using PSR/PR.
v3: dsb_commit as a first parameter
v2: use intel_psr_trigger_frame_change_event
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-13-jouni.hogander@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions