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authorIcenowy Zheng <icenowy@aosc.io>2019-07-28 11:12:26 +0800
committerMaxime Ripard <maxime.ripard@bootlin.com>2019-08-23 09:14:48 +0200
commitd400cc4ad18f55a8253b2694f5594738e5cfacc2 (patch)
tree2ea1113676fe8668a5411dc0639242a189b7f7ec /tools/perf/scripts/python/export-to-postgresql.py
parent802cbe1b46dca72c922f1ed33333e1d19e4c988e (diff)
dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
The Lichee Zero Plus is a core board made by Sipeed, with a microUSB connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. It has a gold finger connector for expansion, and UART is available from reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or Allwinner V3L SoCs. Add the device tree binding of the basic version of the core board -- w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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