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| author | Imre Deak <imre.deak@intel.com> | 2025-02-14 16:19:54 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-02-14 21:39:06 +0200 |
| commit | dc2b12b34fb8070b304a8725c4c4060058bc6ab7 (patch) | |
| tree | 371d14b61ee89291d3335f6096a015febaeb6aed /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dcac00e4d6fdddadde1d5147d1f414f467356077 (diff) | |
drm/i915/ddi: Set missing TC DP PHY lane stagger delay in DDI_BUF_CTL
Add the missing PHY lane stagger delay programming for ICL-ADL
platforms on TypeC DP outputs.
v2: (Jani)
- Clarify code comment about lane stagger programming.
- Robustify macro calls with parens.
Bspec: 7534, 49533
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-5-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions