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authorGeert Uytterhoeven <geert+renesas@glider.be>2020-10-01 12:10:05 +0200
committerDavid S. Miller <davem@davemloft.net>2020-10-01 12:53:30 -0700
commit57197b66d0d68dfe7aa612853efd493c79c4ba3a (patch)
treed7121f60881962ec93edcfc3a97c44a00fcfaa5f /tools/perf/scripts/python/export-to-sqlite.py
parent0024bad1f4b19bc11ed40ae3d09d4a83eec209fb (diff)
dt-bindings: net: renesas,ravb: Document internal clock delay properties
Some EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Add properties for configuring the internal MAC delays. These properties are mandatory, even when specified as zero, to distinguish between old and new DTBs. Update the (bogus) example accordingly. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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