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authorBaihan Li <libaihan@huawei.com>2025-03-31 15:42:06 +0800
committerDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>2025-04-11 14:40:00 +0300
commit5f80fb4d6abd1f7f4007e4bf8dd75a8c71d2f724 (patch)
tree3c3c90887606786312eef264d1065cf9c933a810 /tools/perf/scripts/python/export-to-sqlite.py
parent9e736cd444f49efa2334e405f7a59773ea02155b (diff)
drm/hisilicon/hibmc: Add dp serdes cfg in dp process
Add dp serdes cfg in link training process, and related adapting and modificating. Change some init values about training, because we want completely to negotiation process, so we start with the maximum rate and the electrical characteristic level is 0. Because serdes default cfgs is changed and used in hibmc_kms_init(), we changed the if-statement to check whether the value is 0. Signed-off-by: Baihan Li <libaihan@huawei.com> Signed-off-by: Yongbang Shi <shiyongbang@huawei.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250331074212.3370287-4-shiyongbang@huawei.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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