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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2025-07-31 13:43:02 -0700 | 
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2025-07-31 13:43:02 -0700 | 
| commit | cbbf0a759ff96c80dfc32192a2cc427b79447f74 (patch) | |
| tree | a2d1c6fef1c0347581e9f537ff18485a8f65e68c /tools/perf/scripts/python/sched-migration.py | |
| parent | 2d945dde7fa3f17f46349360a9f97614de9f47da (diff) | |
| parent | 9cf9db888f387844e063efc6296e9fa5c042995e (diff) | |
Merge tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull mtd updates from Miquel Raynal:
 "MTD changes:
   - Apart from a binding conversion to yaml, only minor changes/small
     fixes have been merged.
  Raw NAND changes:
   - Minor fixes for various controller drivers like DMA mapping checks,
     better timing derivations or bitflip statistics.
   - some Hynix NAND flashes were not supporting read-retries, so don't
     even try to do it
  SPI NAND changes:
   - In order to support high-speed modes, certain chips need extra
     configuration like adding more dummy cycles. This is now possible,
     especially on Winbond chips.
   - Aside from that, Gigadevice gets support for a new chip (GD5F1GM9).
  SPI NOR changes:
   - A notable changes is the fix for exiting 4-byte addressing on
     Infineon SEMPER flashes. These flashes do not support the standard
     EX4B opcode (E9h), and use a vendor-specific opcode (B8h) instead.
   - There is also a fix for unlocking flashes that are write-protected
     at power-on. This was caused by using an uninitialized mtd_info in
     spi_nor_try_unlock_all()"
* tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (26 commits)
  mtd: spinand: winbond: Add comment about the maximum frequency
  mtd: spinand: winbond: Enable high-speed modes on w35n0xjw
  mtd: spinand: winbond: Enable high-speed modes on w25n0xjw
  mtd: spinand: Add a ->configure_chip() hook
  mtd: spinand: Add a frequency field to all READ_FROM_CACHE variants
  mtd: spinand: Fix macro alignment
  spi: spi-mem: Take into account the actual maximum frequency
  spi: spi-mem: Use picoseconds for calculating the op durations
  mtd: rawnand: atmel: set pmecc data setup time
  mtd: spinand: propagate spinand_wait() errors from spinand_write_page()
  mtd: rawnand: fsmc: Add missing check after DMA map
  mtd: rawnand: rockchip: Add missing check after DMA map
  mtd: rawnand: hynix: don't try read-retry on SLC NANDs
  mtd: rawnand: atmel: Fix dma_mapping_error() address
  mtd: nand: brcmnand: fix mtd corrected bits stat
  mtd: rawnand: renesas: Add missing check after DMA map
  mtd: spinand: gigadevice: Add support for GD5F1GM9 chips
  mtd: nand: brcmnand: replace manual string choices with standard helpers
  mtd: map: Don't use "proxy" headers
  mtd: spi-nor: Fix spi_nor_try_unlock_all()
  ...
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions
