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| author | Yuanfang Zhang <quic_yuanfang@quicinc.com> | 2025-01-16 17:04:20 +0800 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2025-02-26 11:25:05 +0000 |
| commit | 4ff6039ffb79a4a8a44b63810a8a2f2b43264856 (patch) | |
| tree | 51cda016c6ecc92261e671f3faafe4a148cb007c /tools/perf/scripts/python/stackcollapse.py | |
| parent | cade8a89b101dbcd0a169fd464a8dff079d11a2b (diff) | |
coresight-etm4x: add isb() before reading the TRCSTATR
As recommended by section 4.3.7 ("Synchronization when using system
instructions to progrom the trace unit") of ARM IHI 0064H.b, the
self-hosted trace analyzer must perform a Context synchronization
event between writing to the TRCPRGCTLR and reading the TRCSTATR.
Additionally, add an ISB between the each read of TRCSTATR on
coresight_timeout() when using system instructions to program the
trace unit.
Fixes: 1ab3bb9df5e3 ("coresight: etm4x: Add necessary synchronization for sysreg access")
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250116-etm_sync-v4-1-39f2b05e9514@quicinc.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions