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| author | Linu Cherian <lcherian@marvell.com> | 2025-02-12 17:19:14 +0530 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2025-02-21 16:17:20 +0000 |
| commit | 6dbcbcfc4496598c08c87de37456ba618abe59ce (patch) | |
| tree | 7a799b4c345b3941b4c55d4c2e65f839a0cf8772 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 46006ceb5d029f92df405db15c9a31f0ee41628c (diff) | |
coresight: tmc: Enable panic sync handling
- Get reserved region from device tree node for metadata
- Define metadata format for TMC
- Add TMC ETR panic sync handler that syncs register snapshot
to metadata region
- Add TMC ETF panic sync handler that syncs register snapshot
to metadata region and internal SRAM to reserved trace buffer
region.
Signed-off-by: Linu Cherian <lcherian@marvell.com>
Reviewed-by: James Clark <james.clark@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250212114918.548431-5-lcherian@marvell.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions