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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-01-02 18:18:38 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-01-07 17:00:56 +0100 |
| commit | 7e3557b4dd929aee5961417575893a990650e84e (patch) | |
| tree | fcefda83925b9038b03691993948b4f5daa8f301 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 7088d2d7e9a58a972d8c07b4d74837f3c524f2f4 (diff) | |
clk: renesas: r9a09g057: Add reset entry for SYS
Add the missing reset entry for the `SYS` module in the clock driver. The
corresponding core clock entry for `SYS` is already present.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250102181839.352599-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions