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authorAndre Przywara <andre.przywara@arm.com>2025-03-07 00:26:19 +0000
committerChen-Yu Tsai <wens@csie.org>2025-03-12 11:58:09 +0800
commit7cae1e2b5544a6f51972458ec4360c7717ca0145 (patch)
tree89a9db358aaa890ac1ef0053dfb75965033acd75 /tools/perf/scripts/python/syscall-counts.py
parent52dbf84857f051df38f6de3f0c7b7f4506e7ad25 (diff)
clk: sunxi-ng: Add support for the A523/T527 CCU PLLs
Add the PLL clocks of the main CCU of the Allwinner A523 and T527 SoCs. The clocks were modelled after the A523 and T527 manual, and double checked by writing all 1's into the respective register, to spot all implemented bits. The PLL and mod clocks for the two CPU clusters and the DSU are part of a separate CCU, also most audio clocks are collected in a DSP CCU, so both of these clock groups are missing from this driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-6-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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