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| author | Andre Przywara <andre.przywara@arm.com> | 2025-03-07 00:26:17 +0000 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2025-03-12 11:58:09 +0800 |
| commit | e16b9b71f40f603d5cbdcf02007c05ee03cb2be7 (patch) | |
| tree | 02724782b5507a753d5c23d064153caabf98f7b8 /tools/perf/scripts/python/syscall-counts.py | |
| parent | cdbb9d0d09db4cd09d23fec02d3b458664bc3d38 (diff) | |
clk: sunxi-ng: Add support for update bit
Some clocks in the Allwinner A523 SoC contain an "update bit" (bit 27),
which must be set to apply any register changes, namely the mux
selector, the divider and the gate bit.
Add a new CCU feature bit to mark those clocks, and set bit 27 whenever
we are applying any changes.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307002628.10684-4-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions