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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-01-29 12:55:04 +0100 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2025-02-26 12:15:48 +0200 |
| commit | baf49072877726616c7f5943a6b45eb86bfeca0a (patch) | |
| tree | 9beadd9dd92e7d6f5a298df4633ae2c6e22574de /tools/perf/scripts/python/task-analyzer.py | |
| parent | 5100ae76b5ab6afab33f38bc5850da2d076e5732 (diff) | |
drm/msm/dsi/phy: Program clock inverters in correct register
Since SM8250 all downstream sources program clock inverters in
PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as
reset value (0x0). The most recent Hardware Programming Guide for 3 nm,
4 nm, 5 nm and 7 nm PHYs also mention PLL_CLOCK_INVERTERS_1.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reported-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/634489/
Link: https://lore.kernel.org/r/20250129115504.40080-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions