diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-02-08 00:31:55 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-02-12 19:21:42 +0200 |
| commit | c9178dfba53ffd055c35f0daea9c35de89b45219 (patch) | |
| tree | 2fbac8d995d297afbee1ae4cd3cc8d326c5d8e21 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 51385d68990cca5263ab9575edd5386f6e42a994 (diff) | |
drm/i915/dsb: Compute use_dsb earlier
Skip all the commit completion interrupt stuff on the
chained DSB when we don't take the full DSB path (ie. when
the plane/pipe programming is done via MMIO). The commit
completion will be done via the CPU side vblank interrupt.
Currently this is just a redundant interrupt, so not a big
deal. But in the future we'll be moving the TRANS_PUSH write
into the chained DSB as well, and that we definitely don't
want to do when it's also being done by the CPU from
intel_pipe_update_end().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250207223159.14132-5-ville.syrjala@linux.intel.com
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions