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authorVille Syrjälä <ville.syrjala@linux.intel.com>2022-04-13 22:26:07 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2022-06-27 18:31:51 +0300
commit3cdcdc34f35eb4616f7e5954cbdcd3390da8eae4 (patch)
treee15ed90c7decb958be452aad3e8a70f072d06a9f /tools/perf/scripts/python
parent138c2fca6f408f397ea8fbbbf33203f244d96e01 (diff)
drm/i915: Eliminate PIPECONF RMWs from .color_commit()
Eliminate the PIPECONF RMWs from .comit_commit() so that we can finally declare the whole vblank evade part (and the noarm() part) of the pipe commit free of register reads. Or at least I hope that's the last read... Only the i9xx/ilk codepaths need this for now, but let's add the same thing for hsw+ just in case we want to start calling that during fastsets at some point (eg. to change dithering settings/etc.). Should open up the way to start experimenting with different DSB usage approaches for pipe commits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220413192607.27533-1-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions