diff options
| author | Satheeshakrishna M <satheeshakrishna.m@intel.com> | 2014-11-13 14:55:19 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-11-14 11:18:46 +0100 |
| commit | efa80add54d12bdeba996220463b6ee4ff6b81ae (patch) | |
| tree | 9f2515d34f39ea77ee237e55f7bf02dc83d36c5c /tools/perf/scripts/python | |
| parent | d1a2dc7835f1258ac91cbdd8da1bc97b029b80f7 (diff) | |
drm/i915/skl: Adjust the port PLL selection code
Skylake deprecates the usage of PORT_CLK_SEL and we are advised to use
the new DPLL_CRTL2 for the DDI->PLL mapping.
v2: Modified as per review comments
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions