diff options
Diffstat (limited to 'drivers/soc/renesas')
| -rw-r--r-- | drivers/soc/renesas/Kconfig | 11 | ||||
| -rw-r--r-- | drivers/soc/renesas/Makefile | 1 | ||||
| -rw-r--r-- | drivers/soc/renesas/r9a09g056-sys.c | 75 | ||||
| -rw-r--r-- | drivers/soc/renesas/rz-sysc.c | 3 | ||||
| -rw-r--r-- | drivers/soc/renesas/rz-sysc.h | 1 |
5 files changed, 91 insertions, 0 deletions
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 4990b85d7df7..fbc3b69d21a7 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -393,6 +393,13 @@ config ARCH_R9A09G047 help This enables support for the Renesas RZ/G3E SoC variants. +config ARCH_R9A09G056 + bool "ARM64 Platform support for RZ/V2N" + default y if ARCH_RENESAS + select SYS_R9A09G056 + help + This enables support for the Renesas RZ/V2N SoC variants. + config ARCH_R9A09G057 bool "ARM64 Platform support for RZ/V2H(P)" default y if ARCH_RENESAS @@ -439,6 +446,10 @@ config SYS_R9A09G047 bool "Renesas RZ/G3E System controller support" if COMPILE_TEST select SYSC_RZ +config SYS_R9A09G056 + bool "Renesas RZ/V2N System controller support" if COMPILE_TEST + select SYSC_RZ + config SYS_R9A09G057 bool "Renesas RZ/V2H System controller support" if COMPILE_TEST select SYSC_RZ diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 81d4c5726e4c..3bdcc6a395d5 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o obj-$(CONFIG_SYS_R9A09G047) += r9a09g047-sys.o +obj-$(CONFIG_SYS_R9A09G056) += r9a09g056-sys.o obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o # Family diff --git a/drivers/soc/renesas/r9a09g056-sys.c b/drivers/soc/renesas/r9a09g056-sys.c new file mode 100644 index 000000000000..3ad1422eba36 --- /dev/null +++ b/drivers/soc/renesas/r9a09g056-sys.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/V2N System controller (SYS) driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/io.h> + +#include "rz-sysc.h" + +/* Register Offsets */ +#define SYS_LSI_MODE 0x300 +#define SYS_LSI_MODE_SEC_EN BIT(16) +/* + * BOOTPLLCA[1:0] + * [0,0] => 1.1GHZ + * [0,1] => 1.5GHZ + * [1,0] => 1.6GHZ + * [1,1] => 1.7GHZ + */ +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) +#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 + +#define SYS_LSI_PRR 0x308 +#define SYS_LSI_PRR_GPU_DIS BIT(0) +#define SYS_LSI_PRR_ISP_DIS BIT(4) + +#define SYS_RZV2N_FEATURE_G31 BIT(0) +#define SYS_RZV2N_FEATURE_C55 BIT(1) +#define SYS_RZV2N_FEATURE_SEC BIT(2) + +static void rzv2n_sys_print_id(struct device *dev, + void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr) +{ + u32 prr_val, mode_val; + u8 feature_flags; + + prr_val = readl(sysc_base + SYS_LSI_PRR); + mode_val = readl(sysc_base + SYS_LSI_MODE); + + /* Check GPU, ISP and Cryptographic configuration */ + feature_flags = !(prr_val & SYS_LSI_PRR_GPU_DIS) ? SYS_RZV2N_FEATURE_G31 : 0; + feature_flags |= !(prr_val & SYS_LSI_PRR_ISP_DIS) ? SYS_RZV2N_FEATURE_C55 : 0; + feature_flags |= (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_SEC : 0; + + dev_info(dev, "Detected Renesas %s %sn%d Rev %s%s%s%s%s\n", soc_dev_attr->family, + soc_dev_attr->soc_id, 41 + feature_flags, soc_dev_attr->revision, + feature_flags ? " with" : "", + feature_flags & SYS_RZV2N_FEATURE_G31 ? " GE3D (Mali-G31)" : "", + feature_flags & SYS_RZV2N_FEATURE_SEC ? " Cryptographic engine" : "", + feature_flags & SYS_RZV2N_FEATURE_C55 ? " ISP (Mali-C55)" : ""); + + /* Check CA55 PLL configuration */ + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); +} + +static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initconst = { + .family = "RZ/V2N", + .id = 0x867d447, + .devid_offset = 0x304, + .revision_mask = GENMASK(31, 28), + .specific_id_mask = GENMASK(27, 0), + .print_id = rzv2n_sys_print_id, +}; + +const struct rz_sysc_init_data rzv2n_sys_init_data = { + .soc_id_init_data = &rzv2n_sys_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index 14db508f669f..ffa65fb4dade 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -88,6 +88,9 @@ static const struct of_device_id rz_sysc_match[] = { #ifdef CONFIG_SYS_R9A09G047 { .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sys_init_data }, #endif +#ifdef CONFIG_SYS_R9A09G056 + { .compatible = "renesas,r9a09g056-sys", .data = &rzv2n_sys_init_data }, +#endif #ifdef CONFIG_SYS_R9A09G057 { .compatible = "renesas,r9a09g057-sys", .data = &rzv2h_sys_init_data }, #endif diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index aa83948c5117..56bc047a1bff 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -42,5 +42,6 @@ struct rz_sysc_init_data { extern const struct rz_sysc_init_data rzg3e_sys_init_data; extern const struct rz_sysc_init_data rzg3s_sysc_init_data; extern const struct rz_sysc_init_data rzv2h_sys_init_data; +extern const struct rz_sysc_init_data rzv2n_sys_init_data; #endif /* __SOC_RENESAS_RZ_SYSC_H__ */ |