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path: root/drivers/clk/renesas
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2025-05-08clk: renesas: r9a09g047: Add XSPI clock/resetBiju Das
Add XSPI clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424081400.135028-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08clk: renesas: r9a09g047: Add support for xspi mux and dividerBiju Das
The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and pllcm33_xspi divider to select different clock rates. Add support for both. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424081400.135028-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-05clk: renesas: Use str_on_off() helperGeert Uytterhoeven
Use the str_on_off() helper instead of open-coding the same operation. Note that this does change the case of the flags, which doesn't matter much for debug messages. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/622f8554dcb815c8fc73511a1a118c1724570fa9.1745840497.git.geert+renesas@glider.be
2025-04-22clk: renesas: r9a09g057: Add clock and reset entries for USB2Lad Prabhakar
Add clock and reset entries for USB2. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407165202.197570-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validationLad Prabhakar
Update the clock enable/disable logic to follow the latest hardware manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to confirm the clock state. According to the manual, enabling a clock requires setting the CPG_CLK_ON bit and verifying the clock has started using the CPG_CLK_MON bit. Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and confirming the clock has stopped via the CPG_CLK_MON bit. Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then validate CLK_ON for a more accurate clock status evaluation. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()Lad Prabhakar
Replace hard-coded "ON"/"OFF" strings with the `str_on_off()` helper in `rzv2h_mod_clock_endisable()`. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407165202.197570-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22clk: renesas: rzv2h: Support static dividers without RMWBiju Das
Add support for static dividers that do not require read-modify-write (RMW) operations. This enables the use of the generic clk_divider_ops instead of the custom RMW-based implementation. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407165202.197570-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22clk: renesas: rzv2h: Add macro for defining static dividersLad Prabhakar
Unlike dynamic dividers, static dividers do not have a monitor bit. Introduce the `DEF_CSDIV()` macro for defining static dividers, ensuring consistency with existing dynamic divider macros. Additionally, introduce the `CSDIV_NO_MON` macro to indicate the absence of a monitor bit, allowing the monitoring step to be skipped when `mon` is set to `CSDIV_NO_MON`. Note, `rzv2h_cpg_ddiv_clk_register()` will be re-used instead of generic `clk_hw_register_divider_table()` for registering satic dividers as some of the static dividers require RMW operations. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407165202.197570-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22clk: renesas: rzv2h: Add support for static mux clocksLad Prabhakar
Add support for `CLK_TYPE_SMUX` to register static muxed clocks on the Renesas RZ/V2H(P) SoC. Extend `cpg_core_clk` to include parent names, mux flags, and a new `smuxed` struct. Update clock registration to handle static mux clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407165202.197570-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22clk: renesas: r9a09g047: Add clock and reset entries for GE3DTommaso Merciai
Add CLK_PLLVDO_GPU along with the necessary clock and reset entries for GE3D. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250402131142.1270701-2-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-22clk: renesas: rzv2h: Fix a typoBiju Das
Fix a typo montor->monitor in kernel-doc comment. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250320093107.36784-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14clk: renesas: rzv2h: Add support for RZ/V2N SoCLad Prabhakar
The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present only on the RZ/V2H(P) SoC. Add minimal clock and reset entries required to boot the Renesas RZ/V2N EVK and binds it with the RZ/V2H CPG family driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14clk: renesas: rzv2h: Sort compatible list based on SoC part numberLad Prabhakar
Reorder the compatible entries in `rzv2h_cpg_match[]` to follow a numerical sequence based on the SoC part numbers. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()Tommaso Merciai
rzv2h_cpg_assert() and rzv2h_cpg_deassert() functions are similar. Share this code via __rzv2h_cpg_assert(). This avoid code duplication. Reported-by: Pavel Machek <pavel@denx.de> Closes: https://lore.kernel.org/cip-dev/Z9QA9rwuXCuVbOXp@duo.ucw.cz/ Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250317083213.371614-4-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()Tommaso Merciai
Remove duplicate code into rzv2h_ddiv_set_rate(). Reported-by: Pavel Machek <pavel@denx.de> Closes: https://lore.kernel.org/cip-dev/Z9QBZo4GgtMjid0v@duo.ucw.cz/ Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250317083213.371614-3-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-08clk: renesas: r9a09g057: Add clock and reset entries for GE3DLad Prabhakar
Add PLLGPU along with the necessary clock and reset entries for GE3D. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-08clk: renesas: rzv2h: Rename PLL field macros for consistencyLad Prabhakar
Rename PLL field extraction macros to include the associated register name (`CPG_PLL_CLK1` or `CPG_PLL_CLK2`) to maintain consistency with other PLL register macros. Update all corresponding macro references accordingly. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-08clk: renesas: rzv2h: Add support for enabling PLLsLad Prabhakar
Some RZ/V2H(P) SoC variants do not have a GPU, resulting in PLLGPU being disabled by default in TF-A. Add support for enabling PLL clocks in the RZ/V2H(P) CPG driver to manage this. Introduce `is_enabled` and `enable` callbacks to handle PLL state transitions. With the `enable` callback, PLLGPU will be turned ON only when the GPU node is enabled; otherwise, it will remain off. Define new macros for PLL standby and monitor registers to facilitate this process. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-08clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk`Lad Prabhakar
Remove the redundant `type` field from `struct pll_clk`, as it is not used in the PLL clock handling logic. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-08clk: renesas: rzv2h: Refactor PLL configuration handlingLad Prabhakar
Refactor PLL handling by introducing a `struct pll` to encapsulate PLL configuration parameters, ensuring consistency with the existing dynamic divider structure. Introduce the `PLL_PACK()` macro to simplify PLL structure initialization and update the `DEF_PLL()` macro to use the new `pll` structure. Modify relevant clock register functions to utilize the structured PLL data instead of raw configuration values. This refactoring improves code readability, maintainability, and alignment with the existing clock configuration approach. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-06clk: renesas: r9a09g047: Add clock and reset signals for the TSU IPJohn Madieu
Add required clocks and resets signals for the TSU IP available on the Renesas RZ/G3E SoC Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250227122453.30480-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-06clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1Biju Das
Avoid using the "- 1" for finding mstop_index in all functions accessing priv->mstop_count, by adjusting its pointer in rzv2h_cpg_probe(). While at it, drop the intermediate local variable index. Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Closes: https://lore.kernel.org/all/CAMuHMdX1gPNCFddg_DyK7Bv0BeFLOLi=5eteT_HhMH=Ph2wVvA@mail.gmail.com/ Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250222142009.41324-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-04clk: renesas: r7s9210: Distinguish clocks by clock typeGeert Uytterhoeven
When registering a clock, its type should be devised from the clock's type member, not from its id member. Merge the two checks for the main clock, to improve readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/7e61ea78e9919148e73867088ccbc3509364952e.1740126560.git.geert+renesas@glider.be
2025-03-04clk: renesas: rzg2l: Remove unneeded nullify checksGeert Uytterhoeven
RZ/G2L family clock drivers never had a need to nullify clocks. Remove the unneeded checks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/64702c33396dde2689b44d3e326aa1727ef1557a.1740126560.git.geert+renesas@glider.be
2025-03-04clk: renesas: cpg-mssr: Remove obsolete nullify checkGeert Uytterhoeven
All core clock nullify users and helpers were removed in commit b1dec4e78599a2ce ("clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*"), but the CPG/MSSR driver still checks for nullified core clocks. Remove the obsolete check. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/59ef3eccde0b0b63626480f27e77d5c68948ca98.1740126560.git.geert+renesas@glider.be
2025-03-04clk: renesas: r9a09g057: Add entries for the DMACsFabrizio Castro
Add clock and reset entries for the Renesas RZ/V2H(P) DMAC IPs. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250220150110.738619-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-20clk: renesas: r9a09g047: Add CANFD clocks and resetsBiju Das
Add CANFD clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250218105007.66358-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-20clk: renesas: r9a09g047: Add CRU0 clocks and resetsTommaso Merciai
Add support for CRU0 clocks and resets along with the corresponding divider. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250210114540.524790-2-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-18clk: renesas: rzv2h: Update error messageLad Prabhakar
Update the error message in `rzv2h_mod_clock_endisable()` to provide clearer debugging information. Instead of printing only the register address, include both the `GET_CLK_ON_OFFSET(reg)` offset and the corresponding `clk` name (`%pC`). This enhances readability and aids in debugging clock enable failures. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250211105603.195905-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-18clk: renesas: rzg2l: Update error messageLad Prabhakar
Update the error message in `rzg2l_mod_clock_endisable()` to provide clearer debugging information. Instead of printing only the register address, include both the `CLK_ON_R(reg)` offset and the corresponding `clk` name (`%pC`). This enhances readability and aids in debugging clock enable failures. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250211105603.195905-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a09g047: Add ICU clock/resetBiju Das
Add ICU clock and reset entries. Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250128104714.80807-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a07g043: Fix HP clock source for RZ/FiveLad Prabhakar
According to the Rev.1.20 hardware manual for the RZ/Five SoC, the clock source for HP is derived from PLL6 divided by 2. Correct the implementation by configuring HP as a fixed clock source instead of a MUX. The `CPG_PL6_ETH_SSEL' register, which is available on the RZ/G2UL SoC, is not present on the RZ/Five SoC, necessitating this change. Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Cc: stable@vger.kernel.org Reported-by: Hien Huynh <hien.huynh.px@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250127173159.34572-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a09g047: Add SDHI clocks/resetsBiju Das
Add SDHI[0-2] clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250126134616.37334-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779h0: Add VSPX clockNiklas Söderlund
Add the VSPX modules clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115175927.3714357-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779h0: Add FCPVX clockNiklas Söderlund
Add the FCPVX modules clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115175927.3714357-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a08g045: Check the source of the CPU PLL settingsClaudiu Beznea
On the RZ/G3S SoC, the CPU PLL settings can be set and retrieved through the CPG_PLL1_CLK1 and CPG_PLL1_CLK2 registers. However, these settings are applied only when CPG_PLL1_SETTING.SEL_PLL1 is set to 0. Otherwise, the CPU PLL operates at the default frequency of 1.1 GHz. Hence add support to the PLL driver for returning the 1.1 GHz frequency when the CPU PLL is configured with the default frequency. Fixes: 01eabef547e6 ("clk: renesas: rzg2l: Add support for RZ/G3S PLL") Fixes: de60a3ebe410 ("clk: renesas: Add minimal boot support for RZ/G3S SoC") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115142059.1833063-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a09g047: Add WDT clocks and resetsBiju Das
WDT0 reset is for CM33. Add WDT[1-3] clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115103858.104709-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779h0: Add ISP core clocksNiklas Söderlund
Add the ISP core module clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250114183005.2761213-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779g0: Add ISP core clocksNiklas Söderlund
Add the ISP core modules clock for Renesas R-Car V4H. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250114183005.2761213-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779a0: Add ISP core clocksNiklas Söderlund
Add the ISP core modules clock for Renesas R-Car V3U. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250114183005.2761213-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r8a779a0: Add FCPVX clocksNiklas Söderlund
Add the FCPVX modules clock for Renesas R-Car V3U. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250109125036.2399199-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a07g044: Add clock and reset entry for DRP-AILad Prabhakar
Add clock and reset entries for the DRP-AI block, which is available only on the Renesas RZ/V2L SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250106202853.262787-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ↵Claudiu Beznea
TSU IP Add clocks, resets and power domains for the TSU IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250103163805.1775705-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validationLad Prabhakar
Refactor rzg2l_cpg_attach_dev to delegate clock validation for Runtime PM to the updated rzg2l_cpg_is_pm_clk function. Ensure validation of clocks associated with the power domain while excluding external and core clocks. Prevent incorrect Runtime PM management for clocks outside the domain's scope. Update rzg2l_cpg_is_pm_clk to operate on a per-power-domain basis. Verify clkspec.np against the domain's device node, check argument validity, and validate clock type (CPG_MOD). Use the no_pm_mod_clks array to exclude specific clocks from PM management. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241216210201.239855-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g057: Add clock and reset entries for GICLad Prabhakar
Add clock and reset entries for GIC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250102181839.352599-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g057: Add reset entry for SYSLad Prabhakar
Add the missing reset entry for the `SYS` module in the clock driver. The corresponding core clock entry for `SYS` is already present. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250102181839.352599-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r8a779g0: Add VSPX clocksJacopo Mondi
Add the VSPX modules clock for Renesas R-Car V4H (R8A779G0) SoC. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com> Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-3-7dc1812585ad@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r8a779g0: Add FCPVX clocksJacopo Mondi
Add the FCPVX modules clock for Renesas R-Car V4H (R8A779G0) SoC. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com> Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-1-7dc1812585ad@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g047: Add I2C clocks/resetsBiju Das
Add I2C{0..8} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241216120029.143944-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g047: Add CA55 core clocksBiju Das
Add CA55 core clocks which are derived from PLLCA55. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/20241213123550.289193-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2025-07-16 11:22:07 +0000