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path: root/drivers/gpu/drm/amd/include/asic_reg
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2025-05-13drm/amdgpu: add vcn v5_0_0 ip headersfanhuang
Add vcn v5_0_0 register offset and shift masks header files Only include the registers required for MMSCH initialization Signed-off-by: fanhuang <FangSheng.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-04-07drm/amdgpu: add missing SMU6 defines, shifts and masksAlexandre Demers
They will be used later when switching away from sid.h/si_enums.h. Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-04-07drm/amdgpu: keep removing sid.h dependency from si_dma.cAlexandre Demers
Move and rename DMA_SEM_INCOMPLETE_TIMER_CNTL and DMA_SEM_WAIT_FAIL_TIMER_CNTL in oss_1_0_d.h Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-04-07drm/amdgpu: add missing GFX6 definesAlexandre Demers
They will be used later when switching away from sid.h/si_enums.h. v2: fix whitespace (Alex) Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-04-07drm/amdgpu: add missing DMA defines, shifts and masksAlexandre Demers
They will be used later when switching away from sid.h/si_enums.h. v2: fix up whitespace (Alex) Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-04-07drm/amdgpu: use proper defines, shifts and masks in DCE6 codeAlexandre Demers
By replacing VGA_VSTATUS_CNTL by VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK, we also need to fix its usage in GMC6. Note: VGA_VSTATUS_CNTL's binary value was inverted in dce_6_0_sh_mask.h, so we need to invert its value where it was used. Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-03-07drm/amdkfd: Add support for more per-process flagHarish Kasiviswanathan
Add support for more per-process flags starting with option to configure MFMA precision for gfx 9.5 v2: Change flag name to KFD_PROC_FLAG_MFMA_HIGH_PRECISION Remove unused else condition v3: Bump the KFD API version v4: Missed SH_MEM_CONFIG__PRECISION_MODE__SHIFT define. Added it. Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-03-07drm/amd/amdgpu: Add missing GC 11.5.0 registerTom St Denis
Adds register needed for debugging purposes. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-19drm/amdgpu: Add JPEG4_0_3 core reset control regSathishkumar S
Add core reset control registers for JPEG4_0_3 Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12drm/amdgpu: Set snoop bit for SDMA for MI seriesHarish Kasiviswanathan
SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for this to happen. v2: Missed a few mmhub_v9_4. Added now. v3: Calculate hub offset once since it doesn't change inside the loop Modified function names based on review comments. Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12drm/amd/display: Add dcn36 register header filesWayne Lin
[Why & How] Add register headers for DCN36. V2: adjust copyright license text Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-02-12drm/amdgpu: Add VCN v4.0.3 RRMT register offsetLijo Lazar
Add RRMT control register offset for VCN v4.0.3 Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-12-10drm/amdgpu: rename register headers to dcn_2_0_1Leo Li
They were named with the incorrect dcn version. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Sun peng Li <sunpeng.li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-12-10drm/amdgpu: Add umc v8_14_0 ip headersCandice Li
Add umc v8_14_0 ip headers. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-11-20drm/amd: Add some missing straps from NBIO 7.11.0Mario Limonciello
Earlier ASICs have strap information exported, and this is missing for NBIO 7.11.0. Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Fixes: ca8c68142ad8 ("drm/amdgpu: add nbio 7.11 registers") Link: https://lore.kernel.org/r/20241118174611.10700-1-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-11-04drm/amd/display: Add a missing DCN401 reg definitionAurabindo Pillai
Add a mising reg field to the autogenerated header for future use Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-10-22drm/amdgpu: init saw registers for mmhub v1.0Zhu Lingshan
This commits init registers in the Stand Along Walker for mmhub v1.0, to support ISP use cases. Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com> Reported-and-tested-by: Du Bin <bin.du@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-08-13drm/amdgpu/uvd4: fix mask and shift definitionsRemington Brasga
A few define's are listed twice with different, incorrect values. This fix sets them appropriately. Signed-off-by: Remington Brasga <rbrasga@uci.edu> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-23drm/amdgpu: Fix atomics on GFX12David Belanger
If PCIe supports atomics, configure register to prevent DF from breaking atomics in separate load/store operations. Signed-off-by: David Belanger <david.belanger@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-27drm/amd: Add some missing register definitionsAurabindo Pillai
Add some register offsets that are required for Display DCC on DCN401 Fixes: 2d072b445622 ("drm/amd: Add reg definitions for DCN401 DCC") Reported-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-27drm/amd: Add reg definitions for DCN401 DCCAurabindo Pillai
[WHAT] Add the necessary register definitions to enable DCC on DCN4x Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-05drm/amdgpu: update gc_12_0_0 headersAlex Deucher
Add some additional registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Add missing registers for DCN401Rodrigo Siqueira
Add some additional registers. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-23drm/amdgpu: Add missing offsets in gc_11_0_0_offset.hSunil Khatri
IB1 registers: regCP_IB1_CMD_BUFSZ regCP_IB1_BASE_LO regCP_IB1_BASE_HI regCP_IB1_BUFSZ regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR Above registers are part of the asic but not of the offset file for gc_11_0_0_offset.h and hence adding them. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-20drm/amd/amdgpu: add thm 14.0.2 header fileKenneth Feng
add thm 14.0.2 header file v2: add license, update to latest changes (Alex) Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com>
2024-04-30drm/amdgpu: Add mmhub v4_1_0 ip headers (v4)Hawking Zhang
v1: Add mmhub v4_1_0 register offset and shift masks header files. (Hawking) v2: Update mmhub v4_1_0 register offset and shift masks header files to RE2. (Likun) v3: Update mmhub v4_1_0 register offset and shift masks header files to RE2.5 (Likun) v4: Clean up mmhub v4_1_0 ip headers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-30drm/amdgpu: Add gc v12_0_0 ip headers (v4)Hawking Zhang
v1: Add gc v12_0_0 register offset and shift masks header files. (Hawking) v2: Update gc v12_0_0 register offset and shift masks header files to LSD version. (Likun) v3: Update gc v12_0_0 register offset and shift masks header files to RE3 version. (Likun) v4: Updates (Alex) v5: updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-26drm/amd: Add DCN401 related register definitionsAurabindo Pillai
Update register headers. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-26drm/amd/display: Add some missing HDMI registers for DCN3xRodrigo Siqueira
This commit add some missing HDMI control registers to DCN3x. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-26drm/amd/display: Add missing debug registers for DCN2/3/3.1Rodrigo Siqueira
This commit add some missing debug registers for DPCS and RDPC debug. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-26drm/amdgpu: add support of gfx10 register dumpSunil Khatri
Adding gfx10 gc registers to be used for register dump via devcoredump during a gpu reset. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-18drm/amdgpu: add IH_RING1_CFG headers for IH v6.0Sunil Khatri
Add offsets, mask and shift macros for IH v6.0 which are needed to configure ring1 client irq redirection. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-09drm/amd/display: Add missing registersRodrigo Siqueira
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-09drm/amd/display: Add some missing debug registersRodrigo Siqueira
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-03-20drm/amdgpu: Add smuio v14_0_2 ip headers (v4)Hawking Zhang
v1: Add smuio v14_0_2 register offset and shift masks header files. (Hawking) v2: Update smuio v14_0_2 register offset and shift masks header files to RE2. (Likun) v3: Update smuio v14_0_2 register offset and shift masks header files to RE2.5. (Likun) v4: Clean up smuio v14_0_2 ip headers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-03-20drm/amd/display: Add missing registers and offsetRodrigo Siqueira
[Why & How] Registers and offset are missing. Add it back Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-03-20drm/amdgpu: add new bit definitions for GC 9.0 PROTECTION_FAULT_STATUSTao Zhou
Add UCE and FED bit definitions. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-03-07drm/amdgpu: Add pcie v6_1_0 ip headers (v5)Hawking Zhang
v1: Add pcie v6_1_0 register offset and shift masks header files. (Hawking) v2: Update pcie v6_1_0 register offset and shift masks header files to RE2. (Likun) v3: Update pcie v6_1_0 register offset and shift masks header files to RE2.5. (Likun) v4: Update pcie v6_1_0 register offset and shift masks header files to RE3. (Likun) v5: Updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-03-07drm/amdgpu: Add nbif v6_3_1 ip headers (v5)Hawking Zhang
v1: Add nbif v6_3_1 register offset and shift masks header files. (Hawking) v2: Update nbif v6_3_1 register offset and shift masks header files to RE2. (Likun) v3: Update nbif v6_3_1 register offset and shift masks header files to RE2.5. (Likun) v4: Update nbif v6_3_1 register offset and shift masks header files to RE3. (Likun) v5: Updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-03-04drm/amd: add register headers for DCN351Hamza Mahfooz
Add register headers for DCN 3.5.1. Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-02-22Revert "drm/amdgpu: Add pci usage to nbio v7.9"Asad Kamal
Remove implementation to get pcie usage for nbio v7.9 as pcie usage is handled by fw This reverts commit 59070fd9ccea58c3363d39f69c25fa98c71eb02f. Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-02-16drm/amdgpu/nbio: Add NBIO 7.11.1 SupportYifan Zhang
Fix up doorbell setup and clockgating. v2: squash in fixes (Alex) Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-02-14drm/amdgpu: Add mp v14_0_2 ip headers (v5)Hawking Zhang
v1: Add mp v14_0_2 register offset and shift masks header files. (Hawking) v2: Update mp v14_0_2 register offset and shift masks header files to RE2. (Likun) v3: Update mp v14_0_2 register offset and shift masks header files to RE2.5. (Likun) v4: Update mp v14_0_2 register offset and shift masks header files to RE3. (Likun) v5: Updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-02-12drm/amdgpu: Add vcn v5_0_0 ip headers (v5)Hawking Zhang
v1: Add vcn v5_0_0 register offset and shift masks header files. (Hawking) v2: Update vcn v5_0_0 register offset and shift masks header files to RE2. (Likun) v3: Update vcn v5_0_0 register offset and shift masks header files to RE2.5. (Likun) v4: Update vcn v5_0_0 register offset and shift masks header files to RE3. (Likun) v5: Clean up vcn v5_0_0 ip headers. (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-02-12drm/amdgpu: Add hdp v7_0_0 ip headers (v3)Hawking Zhang
v1: Add hdp v7_0_0 register offset and shift masks header files (Hawking) v2: Update hdp v7_0_0 register offset and shift masks header files for RE2.5 (Likun) v3: Clean up hdp v7_0_0 ip headers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-02-12drm/amdgpu: Add osssys v7_0_0 ip headers (v4)Hawking Zhang
v1: Add osssys v7_0_0 register offset and shift masks header files. (Hawking) v2: Update osssys v7_0_0 register offset and shift masks header files to RE2. (Likun) v3: Update osssys v7_0_0 register offset and shift masks header files to RE2.5. (Likun) v4: Clean up osssys v7_0_0 ip headers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-02-12drm/amdgpu: Add lsdma v7_0_0 ip headers (v3)Hawking Zhang
v1: Add lsdma v7_0_0 register offset and shift masks header files (Hawking) v2: Update lsdma v7_0_0 register offset and shift masks header files for RE2.5 (Likun) v3: Clean up lsdma v7_0_0 ip headers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-02-12drm/amdgpu: Add athub v4_1_0 ip headers (v5)Hawking Zhang
v1: Add athub v4_1_0 register offset and shift masks header files. (Hawking) v2: Update athub v4_1_0 register offset and shift masks header files to RE2. (Likun) v3: Update athub v4_1_0 register offset and shift masks header files to RE2.5 (Likun) v4: Update athub v4_1_0 register offset and shift masks header files to RE3. (Likun) v5: Clean up athub v4_1_0 ip headers. (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-01-29drm/amd/include: Add missing registers/mask for DCN316 and 350Rodrigo Siqueira
Cc: Jun Lei <Jun.Lei@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-01-15drm/amdgpu: update headers for nbio v7.11Yifan Zhang
This patch is to update headers for nbio v7.11. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-07-16 08:43:04 +0000