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path: root/drivers/irqchip/irq-renesas-rzv2h.c
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2025-02-26irqchip/renesas-rzv2h: Add RZ/G3E supportBiju Das
The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register base offset is 0x800 instead of zero. - The number of GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map. - The number of TSSR registers is 16 instead of 8. - Each TSSR register can program 2 TINTs instead of 4 TINTs. Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and adding LUT for mapping between pin index and TINT selection index. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/all/20250224131253.134199-13-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Update macros ICU_TSSR_TSSEL_{MASK,PREP}Biju Das
On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H. Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved bits is ignored. Use bitmask GENMASK(field_width - 2, 0) on both SoCs for extracting TSSEL and then update the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK for supporting both SoCs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/all/20250224131253.134199-12-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Update TSSR_TIEN macroBiju Das
On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. Replace the macro ICU_TSSR_TIEN(n)->ICU_TSSR_TIEN(n, _field_width) for supporting both these SoCs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/all/20250224131253.134199-11-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Add field_width to struct rzv2h_hw_infoBiju Das
On RZ/G3E the field width for TSSR register for a TINT is 16 compared to 8 on the RZ/V2H. Add field_width to struct rzv2h_hw_info and replace the macros ICU_TSSR_K and ICU_TSSR_TSSEL_N by a runtime evaluation: (32 / field_width) provides the number of tints in the TSSR register. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/all/20250224131253.134199-10-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Add max_tssel to struct rzv2h_hw_infoBiju Das
The number of GPIO interrupts on RZ/G3E for TINT selection is 141 compared to 86 on RZ/V2H. Rename the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL to hold this difference for RZ/V2H. Add max_tssel to struct rzv2h_hw_info and replace the hardcoded constants in the code. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/all/20250224131253.134199-9-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variableBiju Das
The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register base offset is 0x800 instead of zero. - The number of GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map - The number of TSSR registers is 16 instead of 8 - Each TSSR register can program 2 TINTs instead of 4 TINTs Introduce struct rzv2h_hw_info to describe the SoC properties and refactor the code by moving rzv2h_icu_init() into rzv2h_icu_init_common() and pass the variable containing hw difference to support both these SoCs. As a first step add t_offs to the new struct and replace the hardcoded constants in the code. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/all/20250224131253.134199-8-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Use devm_pm_runtime_enable()Biju Das
Simplify rzv2h_icu_init() by using devm_pm_runtime_enable(). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/all/20250224131253.134199-7-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Use devm_reset_control_get_exclusive_deasserted()Biju Das
Use devm_reset_control_get_exclusive_deasserted() to simplify rzv2h_icu_init(). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/all/20250224131253.134199-6-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()Biju Das
Use devm_add_action_or_reset() for calling put_device in error path of rzv2h_icu_init() to simplify the code by using the recently added devm_* helpers. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/all/20250224131253.134199-5-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_privBiju Das
Use rzv2h_icu_chip directly on irq_domain_set_hwirq_and_chip() and drop the global variable irqchip from struct rzv2h_icu_priv. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/all/20250224131253.134199-4-biju.das.jz@bp.renesas.com
2025-02-26irqchip/renesas-rzv2h: Fix wrong variable usage in rzv2h_tint_set_type()Biju Das
The variable tssel_n is used for selecting TINT source and titsel_n for setting the interrupt type. The variable titsel_n is wrongly used for enabling the TINT interrupt in rzv2h_tint_set_type(). Fix this issue by using the correct variable tssel_n. While at it, move the tien variable assignment near to tssr. Fixes: 0d7605e75ac2 ("irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20250224131253.134199-3-biju.das.jz@bp.renesas.com Closes: https://lore.kernel.org/CAMuHMdU3xJpz-jh=j7t4JreBat2of2ksP_OR3+nKAoZBr4pSxg@mail.gmail.com
2024-10-16irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driverFabrizio Castro
Add driver for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU). This driver supports the external interrupts NMI, IRQn, and TINTn. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20241009230817.798582-3-fabrizio.castro.jz@renesas.com
generated by cgit (git 2.34.1) at 2025-05-10 05:12:29 +0000