summaryrefslogtreecommitdiff
path: root/include/drm/bridge
AgeCommit message (Collapse)Author
2025-11-14drm/bridge: dw-hdmi-qp: Handle platform supported formats and color depthCristian Ciocaltea
Extend struct dw_hdmi_qp_plat_data to include the supported display output formats and maximum bits per color channel. When provided by the platform driver, use them to setup the HDMI bridge accordingly. Additionally, improve debug logging in dw_hdmi_qp_bridge_atomic_enable() to also show the current HDMI output format and bpc. Acked-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20251021-rk3588-10bpc-v3-2-3d3eed00a6db@collabora.com
2025-10-15drm/bridge: dw-hdmi-qp: Fixup timer base setupCristian Ciocaltea
Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed value as initially found in vendor driver code supporting the RK3588 SoC. As a matter of fact the value matches the rate of the HDMI TX reference clock, which is roughly 428.57 MHz. However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and the incorrect register configuration breaks CEC functionality. Set the timer base according to the actual reference clock rate that shall be provided by the platform driver. Otherwise fallback to the vendor default. While at it, also drop the unnecessary empty lines in dw_hdmi_qp_init_hw(). Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250903-rk3588-hdmi-cec-v4-2-fa25163c4b08@collabora.com
2025-10-15drm/bridge: dw-hdmi-qp: Add CEC supportCristian Ciocaltea
Add support for the CEC interface of the Synopsys DesignWare HDMI QP TX controller. This is based on the downstream implementation, but rewritten on top of the CEC helpers added recently to the DRM HDMI connector framework. Also note struct dw_hdmi_qp_plat_data has been extended to include the CEC IRQ number to be provided by the platform driver. Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Co-developed-by: Derek Foreman <derek.foreman@collabora.com> Signed-off-by: Derek Foreman <derek.foreman@collabora.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250903-rk3588-hdmi-cec-v4-1-fa25163c4b08@collabora.com
2025-10-13Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Updating drm-misc-next to the state of v6.18-rc1. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2025-09-29drm/bridge: imx: add driver for HDMI TX Parallel Audio InterfaceShengjiu Wang
The HDMI TX Parallel Audio Interface (HTX_PAI) is a digital module that acts as the bridge between the Audio Subsystem to the HDMI TX Controller. This IP block is found in the HDMI subsystem of the i.MX8MP SoC. Data received from the audio subsystem can have an arbitrary component ordering. The HTX_PAI block has integrated muxing options to select which sections of the 32-bit input data word will be mapped to each IEC60958 field. The HTX_PAI_FIELD_CTRL register contains mux selects to individually select P,C,U,V,Data, and Preamble. Use component helper so that imx8mp-hdmi-tx will be aggregate driver, imx8mp-hdmi-pai will be component driver, then imx8mp-hdmi-pai can use bind() ops to get the plat_data from imx8mp-hdmi-tx device. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Liu Ying <victor.liu@nxp.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20250923053001.2678596-6-shengjiu.wang@nxp.com
2025-09-29drm/bridge: dw-hdmi: Add API dw_hdmi_set_sample_iec958() for iec958 formatShengjiu Wang
Add API dw_hdmi_set_sample_iec958() for IEC958 format because audio device driver needs IEC958 information to configure this specific setting. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Liu Ying <victor.liu@nxp.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20250923053001.2678596-5-shengjiu.wang@nxp.com
2025-09-29drm/bridge: dw-hdmi: Add API dw_hdmi_to_plat_data() to get plat_dataShengjiu Wang
Add API dw_hdmi_to_plat_data() to fetch plat_data because audio device driver needs it to enable(disable)_audio(). Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Liu Ying <victor.liu@nxp.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20250923053001.2678596-4-shengjiu.wang@nxp.com
2025-09-15drm/bridge: samsung-dsim: add driver support for exynos7870 DSIM bridgeKaustabh Chakraborty
Add support for Exynos7870's DSIM IP block in the bridge driver. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: add ability to define clock names for every variantKaustabh Chakraborty
Presently, all devices refer to clock names from a single array. The only controlling parameter is the number of clocks (num_clks field of samsung_dsim_driver_data) which uses the first n clocks of that array. As new devices are added, this approach turns out to be cumbersome. Separate the clock names in individual arrays required by each variant, in a struct clk_bulk_data. Add a pointer field to the driver data struct which points to their respective clock names, and rework the clock usage code to use the clk_bulk_* API instead. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring the PLL_STABLE bitKaustabh Chakraborty
The PLL_STABLE bit of DSIM_DPHY_STATUS is hardcoded to BIT(31), but Exynos7870's DSIM has it in BIT(24) as per downstream kernel sources. In order to support both, move this bit value to the driver data struct and define it for every driver compatible. Reference the value from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring PLL_M and PLL_S offsetsKaustabh Chakraborty
Currently, PLL_P offset of DSIM_PLLCTRL is configurable in the driver data, while PLL_M and PLL_S offsets are hardcoded as 4-bit and 1-bit offsets respectively, but Exynos7870's DSIM have them at 3-bit and 0-bit offsets as per downstream kernel sources. In order to support both, move both offset values to the driver data struct and define it for every driver compatible. Reference the values from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring the VIDEO_MODE bitKaustabh Chakraborty
The VIDEO_MODE bit of DSIM_CONFIG is hardcoded to BIT(25), but Exynos7870's DSIM has it in BIT(18) as per downstream kernel sources. In order to support both, move this bit value to the driver data struct and define it for every driver compatible. Reference the value from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring the MAIN_VSA offsetKaustabh Chakraborty
The MAIN_VSA offset of DSIM_MSYNC is hardcoded to a 22-bit offset, but Exynos7870's DSIM has it in a 16-bit offset as per the downstream kernel sources. In order to support both, move this offset value to the driver data struct and define it for every driver compatible. Reference the value from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring bits and offsets of CLKCTRL registerKaustabh Chakraborty
DSIM_CLKCTRL bit and offset values hardcoded in the driver: name | bit/offset value --------------------------+----------------- DSIM_LANE_ESC_CLK_EN_CLK | 19 DSIM_LANE_ESC_CLK_EN_DATA | 20 DSIM_BYTE_CLKEN | 24 DSIM_ESC_CLKEN | 28 DSIM_TX_REQUEST_HSCLK | 31 DSIM_CLKCTRL bit and offset values in Exynos7870 DSIM as per downstream kernel sources: name | bit/offset value --------------------------+----------------- DSIM_LANE_ESC_CLK_EN_CLK | 8 DSIM_LANE_ESC_CLK_EN_DATA | 9 DSIM_BYTE_CLKEN | 17 DSIM_ESC_CLKEN | 16 DSIM_TX_REQUEST_HSCLK | 20 In order to support both, move all values to the driver data struct and define it for every driver compatible. Reference the values from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: add flag to control header FIFO waitKaustabh Chakraborty
Exynos7870's DSIM device doesn't require waiting for the header FIFO during a MIPI DSI transfer. Add a flag in the driver data in order to control said behavior. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com
2025-09-15drm/bridge: samsung-dsim: add SFRCTRL registerKaustabh Chakraborty
On Exynos7870 devices, enabling the display requires disabling standby by writing to the SFRCTRL register. Add the register and related bit values. Since this behavior isn't available on other SoCs, implement a flag in the driver data struct indicating the availability of this feature. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: support separate LINK and DPHY status registersKaustabh Chakraborty
Exynos7870's DSIM has separate registers for LINK and DPHY status. This is in contrast to older variants in the driver which use a single register for both. Add a driver data flag which indicates that the device variant supports the legacy status register. Change the register read calls appropriately. Suggested-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-08-28drm/bridge: synopsys: Add DW DPTX Controller support libraryAndy Yan
The DW DP TX Controller is compliant with the DisplayPort Specification Version 1.4 with the following features: * DisplayPort 1.4a * Main Link: 1/2/4 lanes * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps * AUX channel 1Mbps * Single Stream Transport(SST) * Multistream Transport (MST) * Type-C support (alternate mode) * HDCP 2.2, HDCP 1.3 * Supports up to 8/10 bits per color component * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0 * Pixel clock up to 594MHz * I2S, SPDIF audio interface Add library with common helpers to make it can be shared with other SoC. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250822063959.692098-3-andyshrk@163.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-04-21drm/bridge: analogix_dp: Add support for RK3588Damon Ding
Expand enum analogix_dp_devtype with RK3588_EDP, and add max_link_rate and max_lane_count configs for it. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Link: https://lore.kernel.org/r/20250310104114.2608063-11-damon.ding@rock-chips.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-04-21drm/bridge: analogix_dp: Support to get &analogix_dp_device.plat_data and ↵Damon Ding
&analogix_dp_device.aux Add two new functions: one to find &analogix_dp_device.plat_data via &drm_dp_aux, and the other to get &analogix_dp_device.aux. Both of them serve for the function of getting panel from DP AUX bus, which is why they are included in a single commit. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Link: https://lore.kernel.org/r/20250310104114.2608063-6-damon.ding@rock-chips.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2024-12-10drm/bridge/synopsys: Add MIPI DSI2 host controller bridgeHeiko Stuebner
Add a Synopsys Designware MIPI DSI host DRM bridge driver for their DSI2 host controller, based on the Rockchip version from the driver rockchip/dw-mipi-dsi2.c in their vendor-kernel with phy & bridge APIs. While the driver is heavily modelled after the previous IP, the register set of this DSI2 controller is completely different and there are also additional properties like the variable-width phy interface. Tested-by: Daniel Semkowicz <dse@thaumatec.com> Tested-by: Dmitry Yashin <dmt.yashin@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20241209231021.2180582-2-heiko@sntech.de
2024-10-17drm/bridge: synopsys: Add DW HDMI QP TX Controller support libraryCristian Ciocaltea
The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX Controller IP supports the following features, among others: * Fixed Rate Link (FRL) * Display Stream Compression (DSC) * 4K@120Hz and 8K@60Hz video modes * Variable Refresh Rate (VRR) including Quick Media Switching (QMS), aka Cinema VRR * Fast Vactive (FVA), aka Quick Frame Transport (QFT) * SCDC I2C DDC access * TMDS Scrambler enabling 2160p@60Hz with RGB/YCbCr4:4:4 * YCbCr4:2:0 enabling 2160p@60Hz at lower HDMI link speeds * Multi-stream audio * Enhanced Audio Return Channel (EARC) Add library containing common helpers to enable basic support, i.e. RGB output up to 4K@30Hz, without audio, CEC or any HDMI 2.1 specific features. Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20241016-b4-rk3588-bridge-upstream-v10-1-87ef92a6d14e@collabora.com Signed-off-by: Maxime Ripard <mripard@kernel.org>
2024-10-09drm/imx: add forward declarations for typesJani Nikula
The imx.h header does not forward declare the types it uses, and the header is not self-contained. Fix it. Fixes: cc3e8a216d6b ("drm/imx: add internal bridge handling display-timings DT node") Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/20241009140452.1981175-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-03drm/imx: add internal bridge handling display-timings DT nodeDmitry Baryshkov
i.MX DRM DT bindings allow using either a proper panel / bridge graph to provide information about connected panels, or just a display-timings DT node, describing just the timings and the flags. Add helper bridge driver supporting the latter usecase. It will be used by both LDB and parallel-display drivers. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Chris Healy <cphealy@gmail.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> # on imx6q-nitrogen6x Link: https://patchwork.freedesktop.org/patch/msgid/20240602-drm-imx-cleanup-v3-9-e549e2a43100@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-06-27drm/bridge: analogix_dp: remove unused analogix_dp_removeLucas Stach
Now that the clock is handled dynamically through analogix_dp_resume/suspend and it isn't statically enabled in the driver probe routine, there is no need for the remove function anymore. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Robert Foss <rfoss@kernel.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240619182200.3752465-5-l.stach@pengutronix.de
2024-06-27drm/bridge: analogix_dp: remove unused platform power_on_end callbackLucas Stach
This isn't used, but gives the impression of the power on and power off platform calls being non-symmetrical. Remove the unused callback and rename the power_on_start to simply power_on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Robert Foss <rfoss@kernel.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240619182200.3752465-1-l.stach@pengutronix.de
2024-05-22Merge tag 'usb-6.10-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB / Thunderbolt updates from Greg KH: "Here is the big set of USB and Thunderbolt changes for 6.10-rc1. Nothing hugely earth-shattering, just constant forward progress for hardware support of new devices and cleanups over the drivers. Included in here are: - Thunderbolt / USB 4 driver updates - typec driver updates - dwc3 driver updates - gadget driver updates - uss720 driver id additions and fixes (people use USB->arallel port devices still!) - onboard-hub driver rename and additions for new hardware - xhci driver updates - other small USB driver updates and additions for quirks and api changes All of these have been in linux-next for a while with no reported problems" * tag 'usb-6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (154 commits) drm/bridge: aux-hpd-bridge: correct devm_drm_dp_hpd_bridge_add() stub usb: fotg210: Add missing kernel doc description usb: dwc3: core: Fix unused variable warning in core driver usb: typec: tipd: rely on i2c_get_match_data() usb: typec: tipd: fix event checking for tps6598x usb: typec: tipd: fix event checking for tps25750 dt-bindings: usb: qcom,dwc3: fix interrupt max items usb: fotg210: Use *-y instead of *-objs in Makefile usb: phy: tegra: Replace of_gpio.h by proper one usb: typec: ucsi: displayport: Fix potential deadlock usb: typec: qcom-pmic-typec: split HPD bridge alloc and registration usb: musc: Remove unused list 'buffers' usb: dwc3: Wait unconditionally after issuing EndXfer command usb: gadget: u_audio: Clear uac pointer when freed. usb: gadget: u_audio: Fix race condition use of controls after free during gadget unbind. dt-bindings: usb: dwc3: Add QDU1000 compatible usb: core: Remove the useless struct usb_devmap which is just a bitmap MAINTAINERS: Remove {ehci,uhci}-platform.c from ARM/VT8500 entry USB: usb_parse_endpoint: ignore reserved bits usb: xhci: compact 'trb_in_td()' arguments ...
2024-05-11drm/bridge: aux-hpd-bridge: correct devm_drm_dp_hpd_bridge_add() stubDmitry Baryshkov
If CONFIG_DRM_AUX_HPD_BRIDGE is not enabled, the aux-bridge.h header provides a stub for the bridge's functions. Correct the arguments list of one of those stubs to match the argument list of the non-stubbed function. Fixes: e5ca263508f7 ("drm/bridge: aux-hpd: separate allocation and registration") Reported-by: kernel test robot <lkp@intel.com> Cc: stable <stable@kernel.org> Closes: https://lore.kernel.org/oe-kbuild-all/202405110428.TMCfb1Ut-lkp@intel.com/ Cc: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240511-fix-aux-hpd-stubs-v1-1-98dae71dfaec@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-04-05Merge tag 'drm-misc-next-2024-03-28' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next Two misc-next in one. drm-misc-next for v6.10-rc1: The deal of a lifetime! You get ALL of the previous drm-misc-next-2024-03-21-1 tag!! But WAIT, there's MORE! Cross-subsystem Changes: - Assorted DT binding updates. Core Changes: - Clarify how optional wait_hpd_asserted is. - Shuffle Kconfig names around. Driver Changes: - Assorted build fixes for panthor, imagination, - Add AUO B120XAN01.0 panels. - Assorted small fixes to panthor, panfrost. drm-misc-next for v6.10: UAPI Changes: - Move some nouveau magic constants to uapi. Cross-subsystem Changes: - Move drm-misc to gitlab and freedesktop hosting. - Add entries for panfrost. Core Changes: - Improve placement for TTM bo's in idle/busy handling. - Improve drm/bridge init ordering. - Add CONFIG_DRM_WERROR, and use W=1 for drm. - Assorted documentation updates. - Make more (drm and driver) headers self-contained and add header guards. - Grab reservation lock in pin/unpin callbacks. - Fix reservation lock handling for vmap. - Add edp and edid panel matching, use it to fix a nearly identical panel. Driver Changes: - Add drm/panthor driver and assorted fixes. - Assorted small fixes to xlnx, panel-edp, tidss, ci, nouveau, panel and bridge drivers. - Add Samsung s6e3fa7, BOE NT116WHM-N44, CMN N116BCA-EA1, CrystalClear CMT430B19N00, Startek KD050HDFIA020-C020A, powertip PH128800T006-ZHC01 panels. - Fix console for omapdrm. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/bea310a6-6ff6-477e-9363-f9f053cfd12a@linux.intel.com
2024-03-07drm: bridge: samsung-dsim: make samsung-dsim.h self-containedJani Nikula
Include <drm/drm_bridge.h> and forward declare struct platform device. Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9534ca7dfba96580950e116c84ce0fa68fdf93a4.1709749576.git.jani.nikula@intel.com
2024-02-23drm/bridge: aux-hpd: separate allocation and registrationJohan Hovold
Combining allocation and registration is an anti-pattern that should be avoided. Add two new functions for allocating and registering an dp-hpd bridge with a proper 'devm' prefix so that it is clear that these are device managed interfaces. devm_drm_dp_hpd_bridge_alloc() devm_drm_dp_hpd_bridge_add() The new interface will be used to fix a use-after-free bug in the Qualcomm PMIC GLINK driver and may prevent similar issues from being introduced elsewhere. The existing drm_dp_hpd_bridge_register() is reimplemented using the above and left in place for now. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240217150228.5788-3-johan+linaro@kernel.org
2023-12-07drm/bridge: Return NULL instead of plain 0 in drm_dp_hpd_bridge_register() stubNathan Chancellor
sparse complains: drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c: note: in included file: include/drm/bridge/aux-bridge.h:29:16: sparse: sparse: Using plain integer as NULL pointer Return NULL to clear up the warning. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312060025.BdeqZrWx-lkp@intel.com/ Fixes: e560518a6c2e ("drm/bridge: implement generic DP HPD bridge") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231205-drm_aux_bridge-fixes-v1-3-d242a0ae9df4@kernel.org
2023-12-04drm/bridge: implement generic DP HPD bridgeDmitry Baryshkov
Several USB-C controllers implement a pretty simple DRM bridge which implements just the HPD notification operations. Add special helper for creating such simple bridges. Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231203114333.1305826-5-dmitry.baryshkov@linaro.org
2023-12-04drm/bridge: add transparent bridge helperDmitry Baryshkov
Define a helper for creating simple transparent bridges which serve the only purpose of linking devices into the bridge chain up to the last bridge representing the connector. This is especially useful for DP/USB-C bridge chains, which can span across several devices, but do not require any additional functionality from the intermediate bridges. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231203114333.1305826-2-dmitry.baryshkov@linaro.org
2023-10-16drm/bridge: synopsys: dw-mipi-dsi: Add mode fixup supportLiu Ying
Vendor drivers may need to fixup mode due to pixel clock tree limitation, so introduce the ->mode_fixup() callcack to struct dw_mipi_dsi_plat_data and call it at atomic check stage if available. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Robert Foss <rfoss@kernel.org> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230821034008.3876938-5-victor.liu@nxp.com
2023-10-16drm/bridge: synopsys: dw-mipi-dsi: Add input bus format negotiation supportLiu Ying
Introduce ->get_input_bus_fmts() callback to struct dw_mipi_dsi_plat_data so that vendor drivers can implement specific methods to get input bus formats for Synopsys DW MIPI DSI. While at it, implement a generic callback for ->atomic_get_input_bus_fmts(), where we try to get the input bus formats through pdata->get_input_bus_fmts() first. If it's unavailable, fall back to the only format - MEDIA_BUS_FMT_FIXED, which matches the default behavior if ->atomic_get_input_bus_fmts() is not implemented as ->atomic_get_input_bus_fmts()'s kerneldoc indicates. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Robert Foss <rfoss@kernel.org> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230821034008.3876938-3-victor.liu@nxp.com
2023-10-16drm/bridge: synopsys: dw-mipi-dsi: Add dw_mipi_dsi_get_bridge() helperLiu Ying
Add dw_mipi_dsi_get_bridge() helper so that it can be used by vendor drivers which implement vendor specific extensions to Synopsys DW MIPI DSI. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Robert Foss <rfoss@kernel.org> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230821034008.3876938-2-victor.liu@nxp.com
2023-10-09drm/bridge: samsung-dsim: update PLL reference clockMichael Tretter
The PLL requires a clock frequency in a certain platform-dependent range after the pre-divider. The reference clock for the PLL may change due to changes to it's parent clock. Thus, the frequency may be out of range or unsuited for generating the high speed clock for MIPI DSI. Try to keep the pre-devider small, and set the reference clock close to the upper limit before recalculating the PLL configuration. Use a divider with a power of two for the reference clock as this seems to work best in my tests. Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20230818-samsung-dsim-v2-3-846603df0e0a@pengutronix.de Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230818-samsung-dsim-v2-3-846603df0e0a@pengutronix.de
2023-10-09drm/bridge: samsung-dsim: reread ref clock before configuring PLLMichael Tretter
The PLL reference clock may change at runtime when its parent clock changes. For example, this may happen on the i.MX8M Nano if the reference clock is a child of the Video PLL. If the pixel clock changes, this may propagate to the Video PLL and as a side effect change the reference clock. Thus, reading the clock rate during probe is not sufficient to correctly configure the PLL for the expected hs clock. Read the actual rate of the reference clock before calculating the PLL configuration parameters. Note that the "samsung,pll-clock-frequency" is always preferred and PLL reference clock is only read from the clock tree if that device tree property is not set. Reviewed-by: Inki Dae <inki.dae@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20230818-samsung-dsim-v2-2-846603df0e0a@pengutronix.de Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230818-samsung-dsim-v2-2-846603df0e0a@pengutronix.de
2023-10-06drm: exynos: dsi: Convert to platform remove callback returning voidUwe Kleine-König
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Eventually after all drivers are converted, .remove_new() is renamed to .remove(). samsung_dsim_remove() returned 0 unconditionally. Make it return void instead to convert the two related platform drivers to use .remove_new(). Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Inki Dae <inki.dae@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Link: https://lore.kernel.org/r/20230919103939.1367659-1-u.kleine-koenig@pengutronix.de Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230919103939.1367659-1-u.kleine-koenig@pengutronix.de
2023-08-11drm: bridge: samsung-dsim: Fix waiting for empty cmd transfer FIFO on older ↵Marek Szyprowski
Exynos Samsung DSIM used in older Exynos SoCs (like Exynos 4210, 4x12, 3250) doesn't report empty level of packer header FIFO. In case of those SoCs, use the old way of waiting for empty command tranfsfer FIFO, removed recently by commit 14806c641582 ("drm: bridge: samsung-dsim: Drain command transfer FIFO before transfer"). Fixes: 14806c641582 ("drm: bridge: samsung-dsim: Drain command transfer FIFO before transfer") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230809145641.3213210-1-m.szyprowski@samsung.com
2023-06-27drm/bridge: dw-hdmi: change YUV420 selection logic at clock setupAdrián Larumbe
Right now clocking value selection code is prioritising RGB, YUV444 modes over YUV420 for HDMI2 sinks. However, because of the bus format selection procedure in dw-hdmi, for HDMI2 sinks YUV420 is the format that will always be picked during the drm bridge chain check stage. Later on dw_hdmi_setup will configure a colour space based on the bus format that doesn't match the pixel value we had calculated as described above. Fix it by bringing back dw-hdmi bus format check when picking the right pixel clock. Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/6230bfae2cd97cf6527fc62ba5c850464919ccf8.1687702042.git.adrian.larumbe@collabora.com
2023-05-26drm: bridge: samsung-dsim: Dynamically configure DPHY timingAdam Ford
The DPHY timings are currently hard coded. Since the input clock can be variable, the phy timings need to be variable too. To facilitate this, we need to cache the hs_clock based on what is generated from the PLL. The phy_mipi_dphy_get_default_config_for_hsclk function configures the DPHY timings in pico-seconds, and a small macro converts those timings into clock cycles based on the hs_clk. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Michael Walle <michael@walle.cc> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # imx8mm-icore Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230526030559.326566-6-aford173@gmail.com
2023-05-26drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp]Adam Ford
According to Table 13-45 of the i.MX8M Mini Reference Manual, the min and max values for M and the frequency range for the VCO_out calculator were incorrect. This information was contradicted in other parts of the mini, nano and plus manuals. After reaching out to my NXP Rep, when confronting him about discrepencies in the Nano manual, he responded with: "Yes it is definitely wrong, the one that is part of the NOTE in MIPI_DPHY_M_PLLPMS register table against PMS_P, PMS_M and PMS_S is not correct. I will report this to Doc team, the one customer should be take into account is the Table 13-40 DPHY PLL Parameters and the Note above." These updated values also match what is used in the NXP downstream kernel. To fix this, make new variables to hold the min and max values of m and the minimum value of VCO_out, and update the PMS calculator to use these new variables instead of using hard-coded values to keep the backwards compatibility with other parts using this driver. Fixes: 4d562c70c4dc ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # imx8mm-icore Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230526030559.326566-3-aford173@gmail.com
2023-05-22drm: bridge: samsung-dsim: Implement support for clock/data polarity swapMarek Vasut
Implement support for DSI clock and data lane DN/DP polarity swap by means of decoding 'lane-polarities' DT property. The controller does support DN/DP swap of clock lane and all data lanes, the controller does not support polarity swap of individual data lane bundles, add a check which verifies all data lanes have the same polarity. This has been validated on an imx8mm board that actually has the MIPI DSI clock lanes inverted. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230514114625.98372-2-festevam@gmail.com
2023-03-28drm: bridge: samsung-dsim: Add i.MX8M Plus supportMarek Vasut
Add extras to support i.MX8M Plus. The main change is the removal of HS/VS/DE signal inversion in the LCDIFv3-DSIM glue logic, otherwise the implementation of this IP in i.MX8M Plus is very much compatible with the i.MX8M Mini/Nano one. Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <m.szyprowski@samsung.com>
2023-03-28drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridgeJagan Teki
Samsung MIPI DSIM controller is common DSI IP that can be used in various SoCs like Exynos, i.MX8M Mini/Nano. In order to access this DSI controller between various platform SoCs, the ideal way to incorporate this in the drm stack is via the drm bridge driver. We already have a consolidated code for supporting component and bridge based DRM drivers, so keep the exynos component based code in existing exynos_drm_dsi.c and move generic bridge code as part of samsung-dsim.c Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2022-04-19drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driverSandor Yu
General Parallel Audio (GPA) interface is one of the supported audio interface for synopsys HDMI module, which has verified for i.MX8MPlus platform. This is initial version for GPA. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/f21ba3e8c4d9d028ac74c6f3c588ddbffe739399.1649989179.git.Sandor.yu@nxp.com
2022-04-19drm: bridge: dw_hdmi: add reset function for PHY GEN1Sandor Yu
PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2, and active low reset control for PHY GEN1. Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset. Add dw_hdmi_phy_gen1_reset function for PHY GEN1. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/e0b3be2d63fe3e95246fb8b8b0dcd57415b29e04.1649989179.git.Sandor.yu@nxp.com
2022-01-04drm/bridge/synopsys: dsi: extend the prototype of mode_valid()Antonio Borneo
To evaluate the validity of a video mode, some additional internal value has to be passed to the platform implementation. Extend the prototype of mode_valid(). Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Reviewed-by: Philippe Cornu <philippe.cornu@foss.st.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20211218215055.212421-2-antonio.borneo@foss.st.com
generated by cgit (git 2.34.1) at 2026-01-01 02:13:09 +0000