diff options
| author | Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> | 2024-08-25 17:41:56 +0530 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2024-08-26 09:57:20 -0700 |
| commit | 037f93434ce9aea3dc19ba2d97e888a12e538f7b (patch) | |
| tree | d6f5bc1a18adf02bb7975523fc049af1001aaef3 | |
| parent | 3126d5fff54368288e7fe1c0fd4ecb36b868e5aa (diff) | |
drm/i915/gt: Whitelist COMMON_SLICE_CHICKEN1 for UMD access.
As part of the recommended tuning setting, whitelist COMMON_SLICE_CHICKEN1
for MTL/ARL and DG2.
The UMD will selectively enable or disable specific bits of the
register based on the type of workload and its requirements.
v2: Remove the KMD par of enabling specific bits(Matt R)
Bspec: 68331
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240825121156.2498810-1-dnyaneshwar.bhadane@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index baa609bdf7cb..e539a656cfc3 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2071,7 +2071,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine) case RENDER_CLASS: /* Required by recommended tuning setting (not a workaround) */ whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); - + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); break; default: break; @@ -2086,7 +2086,7 @@ static void xelpg_whitelist_build(struct intel_engine_cs *engine) case RENDER_CLASS: /* Required by recommended tuning setting (not a workaround) */ whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); - + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); break; default: break; |